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HC05V7GRS/d rev 1.0 68hc05v7 specification rev 1.0 (general release) ? august 12, 1994 mcu system design group oak hill, texas motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part.
HC05V7GRS/d rev 1.0
motorola page iii mc68hc05v7 specification rev. 1.0 table of contents section 1 general description .............................................. 1 1.1 features.................................................................................1 1.2 mask options ........................................................................2 1.3 pin assignments...................................................................2 1.4 mcu structure ....................................................................8 1.5 functional pin description ............................................9 1.5.1 v batt .....................................................................................9 1.5.2 v dd and v ss ........................................................................9 1.5.3 v ssa1 .....................................................................................9 1.5.4 v ssa2 .....................................................................................9 1.5.5 v cca ......................................................................................9 1.5.6 v refh and v refl .................................................................9 1.5.7 osc1, osc2.......................................................................10 1.5.8 reset ................................................................................11 1.5.9 irq (maskable interrupt request) .......................11 1.5.10 pa0-pa7..............................................................................11 1.5.11 pb0-pb5, pb6/tcmp, pb7/tcap ......................................11 1.5.12 pc0-pc7 .............................................................................11 1.5.13 ad0-ad7 / pd0-pd7: ad8-ad15/pe0-pe7 ........................12 1.5.14 pwm....................................................................................12 1.5.15 pf0/ss, pf1/sck, pf2/mosi, pf3/miso .........................12 1.5.16 bus, load, rext1, rext2 ..............................................12 1.5.17 v ign .....................................................................................12 section 2 memory map .............................................................. 13 2.1 single-chip mode memory map .....................................13 2.2 i/o and control registers ............................................13 2.3 ram..........................................................................................14 2.4 rom .........................................................................................15 2.5 eeprom ..................................................................................15 section 3 eeprom ........................................................................ 21 3.1 eeprom programming register $1c ..........................21 3.1.1 cpen - charge pump enable.............................................21 3.1.2 er1:er0 - erase select bits...............................................21 3.1.3 latch.................................................................................22 3.1.4 eerc - eeprom rc oscillator control.............................22 3.1.5 eepgm - eeprom programming power enable...............22 3.2 operation in stop and wait...........................................24
motorola page iv mc68hc05v7 specification rev. 1.0 section 4 cpu core .....................................................................25 4.1 registers............................................................................. 25 4.1.1 accumulator (a) .......................................................... 25 4.1.2 index register (x)........................................................ 25 4.1.3 stack pointer (sp)....................................................... 26 4.1.4 program counter (pc) .............................................. 26 4.1.5 condition code register (ccr).............................. 26 section 5 interrupts .................................................................29 5.1 cpu interrupt processing ........................................... 29 5.2 reset interrupt sequence........................................... 32 5.3 software interrupt (swi) ............................................. 32 5.4 hardware interrupts .................................................... 32 5.5 external interrupt (irq) ............................................... 32 5.5.1 irq control/status register (icsr) $1f ............. 34 5.5.2 external interrupt timing...................................... 36 5.6 16-bit timer interrupt..................................................... 37 5.7 mdlc interrupt.................................................................. 37 5.8 spi interrupt ...................................................................... 37 5.9 8-bit timer interrupt....................................................... 38 section 6 resets..........................................................................39 6.1 external reset (reset) .................................................. 39 6.2 internal resets ................................................................ 40 6.2.1 power-on reset (por)................................................ 40 6.2.2 operation in stop and wait..................................... 40 6.2.3 computer operating properly reset (copr).. 42 6.2.4 low-voltage reset (lvr) .......................................... 43 6.2.5 illegal address ........................................................... 44 6.2.6 disabled stop instruction...................................... 44 section 7 power supply and regulation ........................................ 45 7.1 internal power supply.................................................. 45 7.1.1 primary 5v regulator............................................... 45 7.1.2 secondary regulator.............................................. 45 7.2 miscellaneous register ............................................... 46 7.2.1 igns - ignition status bit ..................................................... 46 7.2.2 oce - output compare enable ........................................... 46 7.2.3 pdc - power down control ................................................ 46 7.3 power moding .................................................................... 47 7.4 regulator control logic ............................................ 49 7.4.1 mask options................................................................. 50 7.5 power supply configuration ..................................... 53 7.5.1 decoupling recommendations.............................. 53
motorola page v mc68hc05v7 specification rev. 1.0 section 8 low-power modes .................................................. 57 8.1 stop instruction ..............................................................57 8.1.1 stop mode .......................................................................57 8.1.2 wait instruction..........................................................59 section 9 parallel i/o............................................................... 61 9.1 port a and port c .............................................................61 9.1.1 port a/c data registers ............................................61 9.1.2 port a/c data direction register..........................62 9.1.3 port a/c i/o pin interrupts.......................................62 9.2 port b ....................................................................................62 9.2.1 port b data register ..................................................63 9.2.2 port b data direction register .............................63 9.3 port d and port e .............................................................63 9.4 port f.....................................................................................64 9.4.1 port f data register ..................................................64 9.4.2 port f data direction register..............................64 section 10 a/d converter......................................................... 65 10.1 analog section..................................................................65 10.1.1 ratiometric conversion ..........................................65 10.1.2 v refh and v refl ...............................................................65 10.1.3 accuracy and precision...........................................65 10.2 conversion process .......................................................65 10.3 digital section...................................................................65 10.4 a/d status and control register (adscr) ..............66 10.5 a/d data registers ...........................................................67 10.6 a/d during wait mode.......................................................68 10.7 a/d during stop mode ......................................................68 section 11 16-bit timer ............................................................... 69 11.1 counter register - $18:$19, $1a:$1b.............................70 11.2 output compare register - $16:$17 ............................70 11.3 input capture register - $14:$15 .................................71 11.4 timer control register (tcr) - $12.............................72 11.4.1 icie - input capture interrupt enable..................................72 11.4.2 ocie - output compare interrupt enable ...........................72 11.4.3 toie - timer overflow interrupt enable..............................72 11.4.4 ton - timer on...................................................................72 11.4.5 iedg - input edge ...............................................................72 11.4.6 olvl - output level............................................................72 11.5 timer status register (tsr) - $13 ................................72 11.5.1 icf - input capture flag......................................................73 11.5.2 ocf - output compare flag ...............................................73 11.5.3 tof - timer overflow flag..................................................73 11.5.4 bits 0-4 - not used...............................................................73
motorola page vi mc68hc05v7 specification rev. 1.0 11.6 timer during wait mode ................................................. 73 11.7 timer during stop mode ................................................ 73 section 12 core timer ................................................................75 12.1 core timer ctrl & status register (ctcsr) $08.... 76 12.1.1 ctof - core timer over flow............................................ 76 12.1.2 rtif - real time interrupt flag .......................................... 76 12.1.3 tofe - timer over flow enable ........................................ 76 12.1.4 rtie - real time interrupt enable...................................... 76 12.1.5 tofc - timer over flow flag clear................................... 76 12.1.6 rtfc - real time interrupt flag clear............................... 77 12.1.7 rt1:rt0 - real time interrupt rate select........................ 77 12.2 computer operating properly (cop) reset.......... 77 12.3 core timer counter register (ctcr) $09 ................ 78 12.4 timer during wait mode ................................................. 78 section 13 pulse width modulator......................................79 13.1 functional description................................................. 79 13.2 registers............................................................................. 81 13.2.1 pwm control................................................................. 81 13.2.2 pwm data registers................................................... 82 13.3 pwm during wait mode.................................................... 82 13.4 pwm during stop mode................................................... 82 13.5 pwm during reset ............................................................ 82 section 14 serial peripheral interface .............................83 14.1 spi signal description.................................................... 83 14.1.1 master in slave out (miso/pf3) ........................................ 84 14.1.2 master out slave in (mosi/pf2) ........................................ 84 14.1.3 serial clock (sck/pf1) ...................................................... 84 14.1.4 slave select (ss/pf0) ........................................................ 85 14.2 functional description................................................. 85 14.3 spi registers...................................................................... 87 14.3.1 serial peripheral control register (spcr) ......................... 87 14.3.2 serial peripheral status register (spsr)........................... 88 14.3.3 serial peripheral data i/o register (spdr) ....................... 89 14.4 spi in stop mode ............................................................... 90 14.5 spi in wait mode ................................................................. 90 section 15 message data link controller.......................91 15.1 outline.................................................................................. 92 15.1.1 mdlc operating modes ............................................. 93 15.1.2 mode descriptions ..................................................... 93 15.2 mdlc cpu interface ......................................................... 95 15.2.1 outline ............................................................................ 95 15.2.2 mdlc control register (mcr) $0e......................... 96 15.2.3 mdlc status register (msr) $0f............................. 99
motorola page vii mc68hc05v7 specification rev. 1.0 15.2.4 mdlc tx control register (mtcr) $10................100 15.2.5 mdlc rx status register (mrsr) $11...................101 15.3 mdlc rx/tx buffers .........................................................103 15.3.1 outline...........................................................................103 15.3.2 rx buffers....................................................................105 15.3.3 tx buffer ......................................................................106 15.4 mdlc protocol handler ..............................................108 15.4.1 outline...........................................................................108 15.4.2 rx & tx shift registers ............................................108 15.4.3 state machine .............................................................109 15.5 mdlc mux interface .......................................................112 15.5.1 rx digital filter..........................................................112 15.5.2 j1850 frame format...................................................114 15.5.3 j1850 vpw symbols .....................................................116 15.5.4 j1850 vpw valid/invalid bits & symbols ..............117 15.5.5 message arbitration ...............................................121 15.6 mdlc physical interface .............................................123 15.6.1 outline...........................................................................123 15.6.2 mux interface signals ............................................126 15.6.3 pins ..................................................................................127 15.7 mdlc application notes ...............................................128 15.7.1 initialization ................................................................128 15.7.2 transmitting a message .........................................128 15.7.3 receiving a message ................................................128 15.7.4 receiving a message in block mode...................129 15.7.5 mdlc stop mode..........................................................130 15.7.6 mdlc wait mode ..........................................................130 15.7.7 controlling external voltage regulators................................................................130 section 16 instruction set .................................................... 133 16.1 register/memory instructions ................................133 16.2 read-modify-write instructions..............................133 16.3 branch instructions.....................................................134 16.4 bit manipulation instructions...................................134 16.5 control instructions ..................................................135 16.6 addressing modes..........................................................135 16.6.1 immediate ......................................................................136 16.6.2 direct .............................................................................136 16.6.3 extended.......................................................................136 16.6.4 relative .........................................................................136 16.6.5 indexed, no offset....................................................136 16.6.6 indexed, 8-bit offset ................................................136 16.6.7 indexed, 16-bit offset ..............................................137 16.6.8 bit set/clear................................................................137 16.6.9 bit test and branch..................................................137 16.6.10 inherent ........................................................................137
motorola page viii mc68hc05v7 specification rev. 1.0 section 17 electrical specifications ................................139 17.1 maximum ratings ............................................................. 139 17.2 thermal characteristics ........................................... 139 17.3 dc electrical characteristics ................................ 140 17.4 regulator electrical characteristics............... 141 17.5 control timing ................................................................ 142 17.6 a/d converter characteristics............................... 143 17.7 dc electrical characteristics ................................ 144 17.8 control timing ................................................................ 145 17.9 lvr timing diagram ......................................................... 146 17.10 spi timing ............................................................................ 147 17.11 mdlc electrical specifications ............................... 150 17.11.1 absolute maximum ratings ................................... 150 17.11.2 operating conditions ............................................. 150 17.11.3 transmitter d.c. electrica characteristics ...................................................... 150 17.11.4 transmitter a.c. electrical characteristics ...................................................... 151 17.11.5 receiver d.c. electrical characteristics ..... 151 17.11.6 transmitter vpw symbol timings ....................... 151 17.11.7 receiver vpw symbol timings .............................. 152 section 18 05v7 behavior during emulation ....................155 18.1 cop........................................................................................ 155 18.2 mdlc ..................................................................................... 155 18.3 regulator ......................................................................... 155
motorola page ix mc68hc05v7 specification rev. 1.0 list of figures figure 1-1: mc68hc05v7 pin assignments (56 pin package)................................3 figure 1-2: mc68hc05v7 pin assignments (68-pin plcc package) .....................4 figure 1-3: mc68hc05v7 pin assignments (64-pin qfp)......................................5 figure 1-4: mc68hc05v7 bonding diagram circuit side up..................................6 figure 1-5: mc68hc05v7 bonding diagram circuit side down .............................7 figure 1-6: mc68hc05v7 block diagram ...............................................................8 figure 1-7: oscillator connections.........................................................................10 figure 2-1: mc68hc05v7 single-chip mode memory map.................................13 figure 2-2: mc68hc05v7 i/o registers memory map .........................................14 figure 2-3: mc68hc05v7 i/o registers $0000-$000f .........................................16 figure 2-4: mc68hc05v7 i/o registers $0010-$001f .........................................17 figure 2-5: mc68hc05v7 i/o registers $0020-$002f .........................................18 figure 2-6: mc68hc05v7 i/o registers $0030-$003f .........................................19 figure 3-1: programming register.........................................................................21 figure 4-1: mc68hc05 programming model ........................................................25 figure 5-1: interrupt processing flowchart............................................................31 figure 5-2: irq function block diagram ...............................................................33 figure 5-3: irq status & control register.............................................................35 figure 5-4: external interrupts timing diagram.....................................................37 figure 6-1: reset block diagram...........................................................................39 figure 6-2: reset and por timing diagram ......................................................41 figure 6-3: cop watchdog timer location...........................................................43 figure 7-1: miscellaneous register .......................................................................46 figure 7-2: mc68hc05v7 power moding flow diagram ......................................48 figure 7-3: regulator startup ................................................................................49 figure 7-4: using the 68hc05v7 with an external regulator................................51 figure 7-5: power moding block diagram .............................................................52 figure 7-6: mc68hc05v7 on-chip power supply configuration ..........................53 figure 7-7: hc705v8 internal power routing .......................................................54 figure 8-1: stop recovery timing diagram...........................................................58 figure 8-2: stop/wait flowcharts.......................................................................59
motorola page x mc68hc05v7 specification rev. 1.0 figure 9-1: port a and port c i/o circuitry ............................................................ 61 figure 9-2: port b i/o circuitry .............................................................................. 63 figure 9-3: port d and port e circuitry.................................................................. 64 figure 10-1: a/d status and control register ......................................................... 66 figure 10-2: a/d data register ............................................................................... 67 figure 11-1: 16-bit timer block diagram ................................................................ 69 figure 11-2: timer control register - $12............................................................... 72 figure 11-3: timer status register - $13 ................................................................ 72 figure 11-4: tcap timing....................................................................................... 74 figure 12-1: core timer block diagram.................................................................. 75 figure 12-2: core timer control and status register ............................................. 76 figure 12-3: timer counter register....................................................................... 78 figure 13-1: pwm block diagram ........................................................................... 79 figure 13-2: pwm waveform examples (pol = 1)................................................. 80 figure 13-3: pwm waveform examples (pol = 0)................................................. 80 figure 13-4: pwm write sequences ....................................................................... 81 figure 13-5: pwm control register ........................................................................ 81 figure 13-6: pwm data register ............................................................................ 82 figure 14-1: data clock timing diagram ................................................................ 84 figure 14-2: serial peripheral interface block diagram .......................................... 86 figure 14-3: serial peripheral interface master-slave interconnection................... 87 figure 14-4: spi control register (spcr) .............................................................. 87 figure 14-5: serial peripheral rate selection ......................................................... 88 figure 14-6: spi status register (spsr)................................................................ 88 figure 15-1: mdlc operating modes state diagram ............................................. 93 figure 15-2: mdlc user registers ......................................................................... 95 figure 15-3: mdlc control register (mcr) ........................................................... 96 figure 15-4: mdlc status register (msr) ............................................................. 99 figure 15-5: mdlc tx control register (mtcr) .................................................. 100 figure 15-6: mdlc rx status register (mrsr) ................................................... 101 figure 15-7: mdlc rx/tx buffers outline............................................................. 105 figure 15-8: mdlc protocol handler outline........................................................ 108 figure 15-9: mdlc rx digital filter block diagram .............................................. 112 figure 15-10: j1850 bus message format (vpw).................................................. 114 figure 15-11: j1850 vpw symbols ........................................................................ 116 figure 15-12: j1850 vpw passive symbols........................................................... 118
motorola page xi mc68hc05v7 specification rev. 1.0 figure 15-13: j1850 vpw eof and ifs symbols...................................................119 figure 15-14: j1850 vpw active symbols ..............................................................120 figure 15-15: j1850 vpw bitwise arbitration..........................................................121 figure 15-16: mdlc physical interface outline.......................................................125 figure 17-1: spi master timing (cpha = 0)....................................................148 figure 17-2: spi master timing (cpha = 1)....................................................148 figure 17-3: spi slave timing (cpha = 0) .......................................................149 figure 17-4: spi slave timing (cpha = 1) .......................................................149 figure 17-5: transmitter a.c. electrical characteristics ........................................151 figure 17-6: variable pulse width modulation (vpw) symbol timings ................153
motorola page xii mc68hc05v7 specification rev. 1.0
motorola page xiii mc68hc05v7 specification rev. 1.0 list of tables table 3-1: erase mode select ..............................................................................22 table 3-2: eeprom write/erase cycle reduction ..............................................23 table 5-1: vector address for interrupts and reset .............................................29 table 6-1: cop watchdog timer recommendations ..........................................43 table 10-1: a/d channel assignments...................................................................67 table 12-1: rti and cop rates at 2.1 mhz ..........................................................77 table 13-1: pwm clock rate .................................................................................81 table 15-1: mdlc transmit abort function summary...........................................97 table 15-2: mdlc rate selection ..........................................................................98 table 15-3: mdlc j1850 bus error summary .....................................................111
motorola page xiv mc68hc05v7 specification rev. 1.0
section 1: general description motorola page 1 mc68hc05v7 specification rev. 1.0 section 1 g eneral description the motorola mc68hc05v7 microcontroller is a custom hc05 based mcu featuring a message data link controller (mdlc) module and on-chip power regulation (rom version of the mc68hc705v8). the device is available packaged in a 56-pin sdip, 68-pin plcc, or 64-pin qfp. a functional block diagram of the mc68hc05v7 is shown in figure 1-6. 1.1 features low cost, hc05 core 10k bytes of user rom 384 bytes of user ram 128 bytes of byte erasable eeprom - byte writeable - byte, block or bulk erasable message data link controller (mdlc) module 16 channel 8-bit a/d converter (8 channels available in 56 sdip version) full function serial peripheral interface (spi) on-chip oscillator for crystal/ceramic resonator 8-bit timer with real time interrupt 16-bit timer with 1 input capture and 1 output compare 38 frequency 6-bit pwm cop watchdog system 22 general purpose i/o pins, 16 with interrupt wake-up capability 6 i/o pins muxed with timer and spi pins. 16 input only pins muxed with a/d. mask option low voltage reset (lvr). on-chip 5v mcu power regulator (mask option to disable) power saving stop and wait mode instructions (mask selectable stop instruction disable)
motorola section 1: general description page 2 mc68hc05v7 specification rev. 1.0 note: a line over a signal name indicates an active low signal. for example, reset is active high and reset is active low. any reference to voltage, current, or frequency specified in the following sections will refer to the nominal values. the exact values and their tolerance or limits are specified in section 17 electrical specifications. 1.2 mask options the following mask options are available: sensitivity on irq interrupt, edge- and level-sensitive or edge-sensitive only selectable cop watchdog system selectable low voltage reset (lvr) selectable stop instruction disable selectable on-chip power supply regulator selectable option to allow regulator wakeup on a rising edge of the mdlc bus selectable option to tie the regulator output to v ss when turned off 1.3 pin assignments the mc68hc05v7 requires 64 bond pads for all i/o and power supply functions. the device is available in a 56-pin sdip package where the 8 a/d channels associated with port e are not bonded out (an8 thru an15). the device is also available in the 68 pin plcc and 64 pin qfp packages. the pin out for the 56-pin sdip, the 68-pin plcc, and the 64-pin qfp packages are shown in the following figures. the pad positions are also in the following figures.
section 1: general description motorola page 3 mc68hc05v7 specification rev. 1.0 . figure 1-1: mc68hc05v7 pin assignments (56-pin package) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 30 31 32 33 34 35 36 37 38 39 40 15 16 17 18 19 20 29 21 22 23 24 25 26 27 28 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 note: this pin assignment is subject to c hang e v ssd v dd osc2 osc1 rst irq pf3/miso pf2/mosi pf1/sclk pf0/ss pb0 pb1 pb2 pb3 pb4 pb5 pb6/tcmp pb7/tcap v ssa2 load bus v batt rext2 rext1 v ign v dd v ssd pd0/an0 pwm pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pd7/an7 pd6/an6 pd5/an5 pd4/an4 pd3/an3 v refl v ssa1 v cca v refh pd2/an2 pd1/an1
motorola section 1: general description page 4 mc68hc05v7 specification rev. 1.0 figure 1-2: mc68hc05v7 pin assignments (68-pin plcc package) rext2 rext1 v ign v dd v ssd pd0/an0 pe0/an8 pe1/an9 pe2/an10 pe3/an11 pd1/an1 pd2/an2 v refh v cca v ssa1 v refl n.c. n.c. i rq rst osc1 osc2 v dd v ssd pwm pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 n.c. pf3/miso pf2/mosi pf1/sclk pf0/ss pb0 pb1 pb2 pb3 pb4 pb5 pb6/tcmp pb7/tcap v ssa2 load bus v batt n.c. pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pe7/an15 pe6/an14 pe5/an13 pe4/an12 pd7/an7 pd6/an6 pd5/an5 pd4/an4 pd3/an3 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 pin numbers
section 1: general description motorola page 5 mc68hc05v7 specification rev. 1.0 figure 1-3: mc68hc05v7 pin assignments (64-pin qfp) rext2 rext1 v ign v dd v ssd pd0/an0 pe0/an8 pe1/an9 pe2/an10 pe3/an11 pd1/an1 pd2/an2 v refh v cca v ssa1 v refl pf3/miso pf2/mosi pf1/sclk pf0/ss pb0 pb1 pb2 pb3 pb4 pb5 pb6/tcmp pb7/tcap v ssa2 load bus v batt pc6 pc5 pc4 pc3 pc2 pc1 pc0 pe7/an15 pe6/an14 pe5/an13 pe4/an12 pd7/an7 pd6/an6 pd5/an5 pd4/an4 pd3/an3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 i rq rst osc1 osc2 v dd v ssd pwm pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 pc7 pin numbers
motorola section 1: general description page 6 mc68hc05v7 specification rev. 1.0 figure 1-4: mc68hc05v7 bonding diagram circuit side up rext2 rext1 v ign v dd v ssd pd0/an0 pe0/an8 pe1/an9 pe2/an10 pe3/an11 pd1/an1 pd2/an2 v refh v cca v ssa1 v refl irq rst osc1 osc2 v dd v ssd pwm pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 pf3/miso pf2/mosi pf1/sclk pf0/ss pb0 pb1 pb2 pb3 pb4 pb5 pb6/tcmp pb7/tcap v ssa2 load bus v batt pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pe7/an15 pe6/an14 pe5/an13 pe4/an12 pd7/an7 pd6/an6 pd5/an5 pd4/an4 pd3/an3
section 1: general description motorola page 7 mc68hc05v7 specification rev. 1.0 figure 1-5: mc68hc05v7 bonding diagram circuit side down v refl v ssa1 v cca v refh pd2/an2 pd1/an1 pe3/an11 pe2/an10 pe1/an9 pe0/an8 pd0/an0 v ssd v dd v ign rext1 rext2 pf3/miso pf2/mosi pf1/sclk pf0/ss pb0 pb1 pb2 pb3 pb4 pb5 pb6/tcmp pb7/tcap v ssa2 load bus v batt pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pe7/an15 pe6/an14 pe5/an13 pe4/an12 pd7/an7 pd6/an6 pd5/an5 pd4/an4 pd3/an3 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pwm v ssd v dd osc2 osc1 rst irq
motorola section 1: general description page 8 mc68hc05v7 specification rev. 1.0 1.4 mcu structure the overall block diagram of the mc68hc05v7 is shown in figure 1-6. figure 1-6: mc68hc05v7 block diagram stk ptr watchdog oscillator cond code reg 1 1 1 i n z c h index reg cpu control 0 0 0 1 1 0 0 0 0 0 reset osc 1 osc 2 sram -384 bytes user rom -10k bytes irq alu 68hc05 cpu accum program counter cpu registers ? 2 pa7 * pa0 * pa1 * pa2 * pa3 * pa4 * pa5 * pa6 * data direction reg port a v ssd * irq interrupt capability 1 eeprom -128 bytes 16-bit timer with 1 ipc & 1 opc pb7/tcap pb0 pb1 pb2 pb3 pb4 pb5 pb6/tcmp data direction reg port b pc7 * pc0 * pc1 * pc2 * pc3 * pc4 * pc5 * pc6 * data direction reg port c mcu power supply regulation v dd lv r v batt 1 channel 38 frequency, 6-bit pwm internal v dd spi pf3/miso pf2/mosi pf1/sclk pwm v ssd 16-channel, 8-bit a/d converter ad0/pd0 ad1/pd1 ad2/pd2 ad3/pd3 ad4/pd4 ad5/pd5 ad6/pd6 ad7/pd7 ad8/pe0 ad9/pe1 ad10/pe2 ad11/pe3 ad12/pe4 ad13/pe5 ad14/pe6 ad15/pe7 v refh v refl mdlc load bus rext2 rext1 v ssa2 e not bonded out 6 -pin sdip pf0/ss interrupt v ssa1 v cca to a/d v cc v ign clkin port f ddr 8-bit timer with rti v dd
section 1: general description motorola page 9 mc68hc05v7 specification rev. 1.0 1.5 functional pin description the following paragraphs give a description of the general function of each pin. 1.5.1 v batt power is supplied to the device through the v batt pin. the on-chip voltage regulator uses this voltage to derive the internal v dd supply for the mcu. the v batt pin is also used to power the mdlc and should still be connected even when the voltage regulator is not used. see section 7 power supply and regulation . 1.5.2 v dd and v ss these pins are provided to allow the internally generated v dd supply to be externally decoupled. the short rise and fall times of the mcu supply current transients place very high short-duration current demands on the internal power supply. to prevent noise problems, special care should be taken to provide good power supply bypassing at the mcu by using bypass capacitors with good high-frequency characteristics that are positioned as close to the mcu supply pins as possible. two sets of v dd and v ss pins are required to maintain on-chip supply noise to within acceptable limits. each supply pin pair will require its own decoupling capacitor. see section 7 power supply and regulation . 1.5.3 v ssa1 v ssa1 is a separate ground pad, which provides a ground return for the a/d subsystem. to prevent digital noise contamination, this pin should be connected directly to a low impedance ground reference point. 1.5.4 v ssa2 v ssa2 is a separate ground pad, which provides a ground return for the mdlc analog subsystem. to prevent digital noise contamination, this pin should be connected directly to a low impedance ground reference point. 1.5.5 v cca v cca is a separate supply pin providing power to the analog subsystems of the mdlc and a/d converter. this pin should be connected to the v dd pin externally. to prevent contamination from the digital supply, this pin should be adequately decoupled to a low impedance ground reference. see section 7 power supply and regulation . 1.5.6 v refh and v refl v refh is the positive (high) reference voltage for the a/d subsystem. v refl is the negative (low) reference voltage for the a/d subsystem. v refh and v refl should be isolated from the digital supplies to prevent any loss of accuracy from the a/d converter.
motorola section 1: general description page 10 mc68hc05v7 specification rev. 1.0 1.5.7 osc1, osc2 the osc1 and osc2 pins are the connections for the on-chip oscillator. osc1 is the input to the oscillator inverter. the output (osc2) will always reflect osc1 inverted except when the device is in stop mode, which forces osc2 high. the osc1, and osc2 pins can accept the following sets of components: 1. a crystal as shown in figure 1-7(a) 2. a ceramic resonator as shown in figure 1-7(a) 3. an external clock signal as shown in figure 1-7(b) the frequency, f osc , of the oscillator or external clock source is divided by two to produce the internal operating frequency, f op . 1.5.7.1 crystal oscillator the circuit in figure 1-7(a) shows a typical oscillator circuit for an at-cut, parallel resonant crystal. the crystal manufacturer? recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable start-up. the load capacitance values used in the oscillator circuit design should include all stray capacitances. the crystal and components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion and radiated emissions. figure 1-7: oscillator connections 1.5.7.2 ceramic resonator oscillator in cost-sensitive applications, a ceramic resonator can be used in place of the crystal. the circuit in figure 1-7(a) is for a ceramic resonator. the resonator manufacturer? recommendations should be followed, as the resonator parameters determine the external component values required for maximum stability and reliable starting. the load capacitance values used in the oscillator circuit design should include all stray capacitances. the ceramic resonator and components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion and radiated emissions. mcu (a) crystal or ceramic resonator connections osc1 osc2 unconnected external clock (b)external clock source connection osc1 osc2 mcu
section 1: general description motorola page 11 mc68hc05v7 specification rev. 1.0 1.5.7.3 external clock an external clock from another cmos-compatible device can be connected to the osc1 input. the osc2 pin should be left unconnected, as shown in figure 1-7(b). 1.5.8 reset this pin can be used as an input to reset the mcu to a known start-up state by pulling it to the low state. the reset pin contains an internal schmitt trigger to improve its noise immunity as an input. the reset pin has an internal pulldown device that pulls the reset pin low when there is an internal cop watchdog reset, por, illegal address reset, a disabled stop instruction reset, or an internal low voltage reset. refer to section 6 resets. 1.5.9 irq (maskable interrupt request) this input pin drives the asynchronous irq interrupt function of the cpu. the irq interrupt function has a mask option to select either negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering. the irq input requires an external resistor to v dd for ?ire-or?operation, if desired. if the irq pin is not used, it must be tied to the v dd supply. the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. each of the pa0 thru pa7 and pc0 thru pc7 i/o pins may be connected as an or function with the irq interrupt function. this capability allows keyboard scan applications where the transitions on the i/o pins will behave the same as the irq pin. the edge or level sensitivity selected by a mask option for the irq pin does not apply to the i/o pin interrupt. the i/o pin interrupt is always negative edge sensitive. see section 5 interrupts for more details on the interrupts. 1.5.10 pa0-pa7 these eight i/o lines comprise port a. the state of any pin is software programmable and all port a lines are configured as inputs during power-on or reset. all eight pins are connected via an internal gate to the irq interrupt function. when the irq interrupt function is enabled, all the port a pins will act as negative edge sensitive irq sources. see section 9 parallel i/o for more details on the i/o ports. 1.5.11 pb0-pb5, pb6/tcmp, pb7/tcap these eight i/o lines comprise port b. the state of any pin is software programmable and all port b lines are configured as inputs during power-on or reset. see section 9 parallel i/o for more details on the i/o ports. pb6 and pb7 are also shared with timer functions. the tcap pin controls the input capture feature for the on-chip 16-bit timer. the tcmp pin provides an output for the output compare feature of the on-chip 16-bit timer. see section 11 16-bit timer for more details on the operation of the timer subsystem. 1.5.12 pc0-pc7 these eight i/o lines comprise port c. the state of any pin is software programmable and all port c lines are configured as inputs during power-on or reset. all eight pins are connected via an internal gate to the irq interrupt function. when the irq interrupt function
motorola section 1: general description page 12 mc68hc05v7 specification rev. 1.0 is enabled, all the port c pins will act as negative edge sensitive irq sources. see section 9 parallel i/o for more details on the i/o ports. 1.5.13 ad0-ad7 / pd0-pd7: ad8-ad15/pe0-pe7 when the a/d converter is disabled, pd0-pd7 and pe0-pe7 are general purpose input pins. the a/d converter is disabled upon exiting from reset. when the a/d converter is enabled, one of these pins is the analog input to the a/d converter. the a/d control register contains control bits to direct which of the analog inputs are to be converted at any one time. a digital read of this pin when the a/d converter is enabled results in a read of logical zero from the selected analog pin. a digital read of the remaining pins gives their correct (digital) values. a/d inputs ad8-ad15 (port e) are not bonded out in the 56-pin package. see section 10 a/d converter for more details on the operation of the a/d subsystem. 1.5.14 pwm this pin provides an output for the pulse width modulation feature of the on-chip programmable timer. see section 13 pulse width modulator for more details on the operation of the pwm subsystem. 1.5.15 pf0/ss , pf1/sck, pf2/mosi, pf3/miso these four i/o lines comprise port f. the state of any pin is software programmable and all port f lines are configured as inputs during power-on or reset. see section 9 parallel i/o for more details on the i/o ports. when the spi subsystem is enabled, pf0- pf3 become the data, clock and select lines for the spi. see section 14 serial peripheral interface for more details on the operation of the spi subsystem. 1.5.16 bus, load, rext1, rext2 these pins provide the i/o interface and external biasing functions for the mdlc subsystem. see section 15 message data link controller for more details on the operation of the mdlc subsystem. the regulator control logic monitors the bus pin and latches a rising edge to re-enable the primary voltage regulator if this mask option is enabled. 1.5.17 v ign the v ign pin is used by the internal voltage regulator power moding circuitry to indicate that the regulator should power up. its state is reflected in the igns bit of the misc register. the input voltage levels on this pin are ratioed to the voltage on v batt . see the electrical specifications. a smaller secondary regulator remains alive to power the v ign pin logic when the primary voltage regulator is powered down, allowing the power moding logic to recognize and latch a rising edge on this pin and re-enable the primary regulator (power- up). see section 7 power supply and regulation for a more detailed description. the v ign pin has no function when the option to disable the on-chip voltage regulator is selected and should be tied low.
section 2: memory map motorola page 13 mc68hc05v7 specification rev. 1.0 section 2 memory map 2.1 single-chip mode memory map when the mc68hc05v7 is in the single-chip mode the i/o and peripherals, user ram, eeprom and user rom are all active as shown in figure 2-1. figure 2-1: mc68hc05v7 single-chip mode memory map 2.2 i/o and control registers the i/o and control registers reside in locations $0000-$003f. the overall organization of these registers is shown in figure 2-2. the bit assignments for each register are shown in 0704 0703 user vectors rom 16 bytes selfcheck/e 2 test rom 512 byes 16383 16368 16367 stack (64 bytes) user ram 192 bytes reset vector (low byte) reset vector (high byte) swi vector (low byte) swi vector (high byte) irq vector (low byte) irq vector (high byte) 16-bit timer vector (low byte) 16-bit timer vector (high byte) $3ff7 $3ff8 $3ff9 $3ffa $3ffb $3ffc $3ffd $3ffe $3fff mdlc (low byte) $003f $0000 $00c0 $00bf 0191 0192 i/o 64 bytes 0064 0063 0000 $3fff $3ff0 $3fef $0040 $003f $0000 user rom 10208 bytes i/o registers 64 bytes (see figure 2- 2 ) $3ff6 mdlc (high byte) $3ff3 8-bit timer (low byte) $3ff4 spi (high byte) $3ff5 spi (low byte) $3ff2 8-bit timer (high byte) $3ff1 unused $3ff0 cop watchdog timer $1600 $15ff user eeprom 128 bytes 5632 5631 unused 4928 bytes $02c0 $02bf $0240 $023f 0575 0576 user ram (128 bytes) unused 128 bytes $01bf $01c0 0447 0448 $00ff $0100 0255 0256 16352 16351 $3fe0 $3fdf selfcheck vectors rom 16 bytes $17ff $1800 6143 6144
motorola section 2: memory map page 14 mc68hc05v7 specification rev. 1.0 figure 2-3, figure 2-4, figure 2-5 and figure 2-6. reading from unimplemented bits will return unknown states, and writing to unimplemented bits will be ignored. figure 2-2: mc68hc05v7 i/o registers memory map 2.3 ram the total ram consists of 384 bytes (including the stack). the stack begins at address $00ff and proceeds down to $00c0 (64 bytes). using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. port a data register port b data register port a data direction register port b data direction register 16-bit timer status register eeprom program register a/d data register a/d status & control register $0000 port c data register port c data direction register alt. count register (low) alt. count register (high) 16 bit timer count register (low) 16 bit timer count register (high) output compare register (low) output compare register (high) input capture register (low) input capture register (high) 16-bit timer control register mdlc rx status register mdlc tx control register mdlc status register mdlc control register spi status register spi control register spi data register port d data register reserved unused port e data register pwm data register miscellaneous register mdlc tx data register 0 mdlc tx data register 1 mdlc tx data register 2 mdlc tx data register 3 mdlc tx data register 4 mdlc tx data register 5 mdlc tx data register 6 mdlc tx data register 7 mdlc tx data register 8 mdlc tx data register 9 mdlc tx data register 10 mdlc rx data register 0 mdlc rx data register 1 mdlc rx data register 2 mdlc rx data register 3 mdlc rx data register 4 mdlc rx data register 5 mdlc rx data register 6 mdlc rx data register 7 mdlc rx data register 8 mdlc rx data register 9 mdlc rx data register10 irq control and status register port f data register port f data direction register unused 8-bit timer status & control unused pwm control register unused unused 8-bit timer counter register $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001a $001b $001c $001d $001e $001f $0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002a $002b $002c $002d $002e $002f $0030 $0031 $0032 $0033 $0034 $0035 $0036 $0037 $0038 $0039 $003a $003b $003c $003d $003e $003f
section 2: memory map motorola page 15 mc68hc05v7 specification rev. 1.0 note: the stack is located in the middle of the ram address space. data written to addresses within the stack address range could be overwritten during stack activity. 2.4 rom there are a total of 10752 bytes of user rom on chip. this includes 10208 bytes of user rom for user program storage, 512 bytes of eeprom test and selfcheck rom, 16 bytes of selfcheck vectors and 16 bytes for user vectors and the cop update location. 2.5 eeprom this device contains 128 bytes of eeprom. programming the eeprom is performed by the user on a single-byte basis by manipulating the programming register, located at address $001c. refer to section 3 eeprom for programming details.
motorola section 2: memory map page 16 mc68hc05v7 specification rev. 1.0 figure 2-3: mc68hc05v7 i/o registers $0000-$000f pa 6 pb6 pc6 pd6 ddra6 ddrb6 ddrc6 rtif d6 spe wcol spd6 txab pa 5 pb5 pc5 pd5 ddra5 ddrb5 ddrc5 tofe d5 spd5 r1 pa 4 pb4 pc4 pd4 ddra4 ddrb4 ddrc4 rtie d4 mstr modf spd4 r0 pa 3 pb3 pc3 pd3 ddra3 ddrb3 ddrc3 tofc d3 cpol spd3 txms pa 2 pb2 pc2 pd2 ddra2 ddrb2 ddrc2 rtfc d2 cpha spd2 rxms pa 1 pb1 pc1 pd1 ddra1 ddrb1 ddrc1 rt1 d1 spr1 spd1 ie pa 0 pb0 pc0 pd0 ddra0 ddrb0 ddrc0 rt0 d0 spr0 spd0 wcm pa 7 pb7 pc7 pd7 ddra7 ddrb7 ddrc7 ctof d7 spie spif spd7 rxbm port a data port b data port c data port d data port a data direction port b data direction port c data direction unused 8 bit timer status/control 8 bit timer counter spi control register spi status register spi data register unused mdlc control register mdlc status register $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f r w r w r w r w r w r w r w r w r w r w r w r w r w r w r w r w addr register 7 6 5 4 3 2 1 0 read write unimplemented one time write
section 2: memory map motorola page 17 mc68hc05v7 specification rev. 1.0 figure 2-4: mc68hc05v7 i/o registers $0010-$001f ocie ocf 14 6 14 6 14 6 14 6 cpen d6 adrc irqpae toie tof 13 5 13 5 13 5 13 5 lvpis d5 adon irqpce 12 4 12 4 12 4 12 4 er1 d4 ch4 tc3 rc3 11 3 11 3 11 3 11 3 er0 d3 ch3 irqf tc2 rc2 ton 10 2 10 2 10 2 10 2 latch d2 ch2 irqpaf tc1 rc1 iedg 9 1 9 1 9 1 9 1 eerc d1 ch1 irqpcf tc0 rc0 olvl 8 0 8 0 8 0 8 0 eepgm d0 ch0 0 irqa icie icf 15 7 15 7 15 7 15 7 lvpi d7 coco irqe mdlc tx control register mdlc rx status register timer control register timer status register input capture high input capture low output compare high output compare low timer counter high timer counter low alt. counter high alt. counter low eeprom programming a/d data a/d status and control irq control and status $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001a $001b $001c $001d $001e $001f r w r w r w r w r w r w r w r w r w r w r w r w r w r w r w r w addr register 7 6 5 4 3 2 1 0 read write unimplemented one time write
motorola section 2: memory map page 18 mc68hc05v7 specification rev. 1.0 figure 2-5: mc68hc05v7 i/o registers $0020-$002f d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 pe7 d7 d7 igns d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 pe0 pf0 d0 ddrf0 pdc d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 pe1 pf1 d1 ddrf1 d1 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 pe2 pf2 d2 ddrf2 d2 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 pe3 pf3 d3 ddrf3 d3 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 pe4 d4 d4 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 pe5 d5 d5 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 pe6 d6 d6 oce mdlc tx data register 0 mdlc tx data register 1 mdlc tx data register 2 mdlc tx data register 3 mdlc tx data register 4 mdlc tx data register 5 mdlc tx data register 6 mdlc tx data register 7 mdlc tx data register 8 mdlc tx data register 9 mdlc tx data register 10 port e data port f data unused port f data direction miscellaneous $0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002a $002b $002c $002d $002e $002f r w r w r w r w r w r w r w r w r w r w r w r w r w r w r w r w addr register 7 6 5 4 3 2 1 0 read write
section 2: memory map motorola page 19 mc68hc05v7 specification rev. 1.0 figure 2-6: mc68hc05v7 i/o registers $0030-$003f d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d3 psb3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d2 psb2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d1 psb1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d0 psb0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d0 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d6 psa0 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 pol psa1 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 pwm data pwm control unused unused mdlc rx data register 0 mdlc rx data register 1 mdlc rx data register 2 mdlc rx data register 3 mdlc rx data register 4 mdlc rx data register 5 mdlc rx data register 6 mdlc rx data register 7 mdlc rx data register 8 mdlc rx data register 9 mdlc rx data register 10 reserved $0030 $0031 $0032 $0033 $0034 $0035 $0036 $0037 $0038 $0039 $003a $003b $003c $003d $003e $003f r w r w r w r w r w r w r w r w r w r w r w r w r w r w r w r w addr register 7 6 5 4 3 2 1 0 read write unimplemented
motorola section 2: memory map page 20 mc68hc05v7 specification rev. 1.0
section 3: eprom and eeprom motorola page 21 mc68hc05v7 specification rev. 1.0 section 3 eeprom the mc68hc05v7 contains eeprom memory. this section describes the programming mechanisms. 3.1 eeprom programming register $1c the contents and use of the programming register are discussed below. figure 3-1: programming register note: any reset including lvr will abort any write in progress when it is asserted. data written to the addressed byte will therefore be indeterminate. 3.1.1 cpen - charge pump enable when set, cpen enables the charge pump which produces the internal programming voltage. this bit should be set with the latch bit. the programming voltage will not be available until eepgm is set. the charge pump should be disabled when not in use. cpen is readable and writable and is cleared by reset. 3.1.2 er1:er0 - erase select bits er1 and er0 form a 2-bit field which is used to select one of three erase modes: byte, block, or bulk. table 3-1 shows the modes selected for each bit configuration. these bits are readable and writable and are cleared by reset. in byte erase mode, only the selected byte is erased. in block mode, a 32-byte block of eeprom is erased. the eeprom memory space is divided into four 32-byte blocks ($0240-$025f, $0260-$027f, $0280-$029f, $02a0-$02bf), and doing a block erase to any address within a block will erase the entire block. in bulk erase mode, the entire 128 byte eeprom section is erased. - - er1 er0 latch eerc eepgm cpen $1c 0 000000 0 reset:
motorola section 3: eprom and eeprom page 22 mc68hc05v7 specification rev. 1.0 table 3-1: erase mode select 3.1.3 latch when set, latch configures the eeprom address and data bus for programming. when latch is set, writes to the eeprom array cause the data bus and the address bus to be latched. this bit is readable and writable, but reads from the array are inhibited if the latch bit is set and a write to the eeprom space has taken place. when clear, address and data buses are configured for normal operation. reset clears this bit. 3.1.4 eerc - eeprom rc oscillator control when this bit is set, the eeprom section uses the internal rc oscillator instead of the cpu clock. after setting the eerc bit, delay a time t rcon to allow the rc oscillator to stabilize. this bit is readable and writable and should be set by the user when the internal bus frequency falls below 1.5 mhz. reset clears this bit. 3.1.5 eepgm - eeprom programming power enable eepgm must be written to enable (or disable) the eepgm function. when set, eepgm turns on the charge pump and enables the programming (or erasing) power to the eeprom array. when clear, this power is switched off. this will enable pulsing of the programming voltage to be controlled internally. this bit can be read at any time, but can only be written to if latch=1. if latch is not set, then eepgm cannot be set. reset clears this bit. 3.1.6 programming/erasing procedures to program a byte of eeprom, set latch = cpen = 1, set er1 = er0 = 0, write data to the desired address, and then set eepgm for a time t eepgm . in general, all bits should be erased before being programmed. however, if write/erase cycling is a concern, a procedure can be followed to minimize the cycling of each bit in each eeprom byte. the erased state is 1; therefore, if any bits within the byte need to be changed from a 0 to a 1, the byte must be erased before programming. the decision 1 er1 0 0 1 1 bulk erase er0 mode 0 no erase 1 byte erase 0 block erase
section 3: eprom and eeprom motorola page 23 mc68hc05v7 specification rev. 1.0 whether to erase a byte before programming is summarized in table 3-2. to erase a byte of eeprom, set latch = 1, cpen = 1, er1 = 0 and er0 = 1, write to the address to be erased, and set eepgm for a time t ebyt . to erase a block of eeprom, set latch = 1, cpen = 1, er1 = 1 and er0 = 0, write to any address in the block, and set eepgm for a time t eblock . for a bulk erase, set latch = 1, cpen = 1, er1 = 1, and er0 = 1, write to any address in the array, and set eepgm for a time t ebulk . to terminate the programming or erase sequence, clear eepgm, delay for a time t fpv to allow the programming voltage to fall, and then clear latch and cpen to free up the buses. following each erase or programming sequence, clear all programming control bits. the following program is an example of the eeprom programming sequence using the timer to implement the required delay and assuming a 2.1 mhz bus frequency. tsr equ $0013 timer status register tcnth equ $0018 timer counter register (high) tcntl equ $0019 timer counter register (low) tcmph equ $0016 timer output compare register (high) tcmpl equ $0017 timer output compare register (low) ocf equ 6 ocf bit of tsr prog equ $001c program register cpen equ 6 charge pump enable er1 equ 4 erase select 1 er0 equ 3 erase select 0 latch equ 2 latch bit eerc equ 1 rc/osc selector eepgm equ 0 ee program bit eestart equ $0240 starting address of eeprom sumpin equ $ff dummy data org $1800 start equ * bset eerc,prog select rc osc bsr delay rc osc stabilization table 3-2: eeprom write/erase cycle reduction eeprom data to be programmed eeprom data before programming erase before programming? 00no 01no 10yes 11no
motorola section 3: eprom and eeprom page 24 mc68hc05v7 specification rev. 1.0 bset cpen,prog turn on charge pump bset latch,prog enable latch bit bclr er1,prog ensure program (not erase) bclr er0,prog ensure program (not erase) lda #sumpin get data sta eestart bset eepgm, prog enable programming power jsr delay wait for program time bclr eepgm,prog clear eepgm jsr delay wait for prog voltage to fall bclr latch,prog clear latch bclr cpen,prog disable charge pump lda #sumpin cmp eestart verify bne out1 clc clear carry bit for no error out rts out1 sec flag an error rts * this routine gives about a 10 ms delay for a 2.1mhz bus. * the same delay routine is used in this example for simplicity, * using the longest delay time. users will want to write shorter * delay routines for applications in which speed is important. delay equ * lda tcnth read ms byte of timer counter add #$15 add offset sta tcmph store back in o/p compare ms byte lda tcntl read ls byte of tcr sta tcmpl store into o/p compare ls byte brclr ocf,tsr,* wait for ocf flag to occur rts 3.2 operation in stop and wait the rc oscillator for the eeprom is automatically disabled when entering stop mode. the user may want to ensure that the rc oscillator is disabled before entering wait mode to help conserve power.
section 4: cpu core motorola page 25 mc68hc05v7 specification rev. 1.0 section 4 cpu core the mc68hc05v7 has a 16k memory map. therefore it uses only the lower 14 bits of the address bus. in the following discussion the upper 2 bits of the address bus can be ignored. also, the stop instruction may be selected to act as either the normal stop instruction or pull a reset by means of a mask option. all other instructions and registers behave as described in this chapter. 4.1 registers the mcu contains five registers that are hard-wired within the cpu and are not part of the memory map. these five registers are shown in figure 4-1 and are described in the following paragraphs. figure 4-1: mc68hc05 programming model 4.1.1 accumulator (a) the accumulator is a general purpose 8-bit register, as shown in figure 4-1. the cpu uses the accumulator to hold operands and results of arithmetic calculations or nonarithmetic operations. the accumulator is unaffected by a reset of the device. 4.1.2 index register (x) the index register shown in figure 4-1 is an 8-bit register that can perform two functions: indexed addressing temporary storage condition code register i accumulator 60 a index register 71 x 4 52 3 stack pointer sp 14 8 15 9 12 13 10 11 pc cc 111 11 0 0 0 0 0 0 0 0 program counter h nzc half-carry bit (from bit 3) interrupt mask negative bit zero bit carry bit 0 0
motorola section 4: cpu core page 26 mc68hc05v7 specification rev. 1.0 in indexed addressing with no offset, the index register contains the low byte of the operand address, and the high byte is assumed to be $00. in indexed addressing with an 8-bit offset, the cpu finds the operand address by adding the index register contents to an 8-bit immediate value. in indexed addressing with a 16-bit offset, the cpu finds the operand address by adding the index register contents to a 16-bit immediate value the index register can also serve as an auxiliary accumulator for temporary storage. the index register is unaffected by a reset of the device. 4.1.3 stack pointer (sp) the stack pointer shown in figure 4-1 is a 16-bit register internally. in devices with memory maps less than 64 kbytes the unimplemented upper address lines are ignored. the stack pointer contains the address of the next free location on the stack. during a reset or the reset stack pointer (rsp) instruction, the stack pointer is set to $00ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. when accessing memory, the ten most significant bits are permanently set to 0000000011. the six least significant register bits are appended to these ten fixed bits to produce an address within the range of $00ff to $00c0. subroutines and interrupts may use up to 64 ($40) locations. if 64 locations are exceeded, the stack pointer wraps around and writes over the previously stored information. a subroutine call occupies two locations on the stack and an interrupt uses five locations. 4.1.4 program counter (pc) the program counter shown in figure 4-1 is a 16-bit register internally. in devices with memory maps less than 64 kbytes the unimplemented upper address lines are ignored. the program counter contains the address of the next instruction or operand to be fetched. normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 4.1.5 condition code register (ccr) the ccr shown in figure 4-1 is a 5-bit register in which four bits are used to indicate the results of the instruction just executed. the fifth bit is the interrupt mask. these bits can be individually tested by a program, and specific actions can be taken as a result of their state. the condition code register should be thought of as having three additional upper bits that are always ones. only the interrupt mask is affected by a reset of the device. the following paragraphs explain the functions of the lower five bits of the condition code register. 4.1.5.1 half carry bit (h-bit) when the half-carry bit is set, it means that a carry occurred between bits 3 and 4 of the accumulator during the last add or adc (add with carry) operation. the half-carry bit is required for binary-coded decimal (bcd) arithmetic operations.
section 4: cpu core motorola page 27 mc68hc05v7 specification rev. 1.0 4.1.5.2 interrupt mask (i-bit) when the interrupt mask is set, the internal and external interrupts are disabled. interrupts are enabled when the interrupt mask is cleared. when an interrupt occurs, the interrupt mask is automatically set after the cpu registers are saved on the stack, but before the interrupt vector is fetched. if an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. normally, the interrupt is processed as soon as the interrupt mask is cleared. a return from interrupt (rti) instruction pulls the cpu registers from the stack, restoring the interrupt mask to its state before the interrupt was encountered. after any reset, the interrupt mask is set and can only be cleared by the clear i-bit (cli), stop, or wait instructions. 4.1.5.3 negative bit (n-bit) the negative bit is set when the result of the last arithmetic operation, logical operation, or data manipulation was negative. (bit 7 of the result was a logical one.) the negative bit can also be used to check an often-tested flag by assigning the flag to bit 7 of a register or memory location. loading the accumulator with the contents of that register or location then sets or clears the negative bit according to the state of the flag. 4.1.5.4 zero bit (z-bit) the zero bit is set when the result of the last arithmetic operation, logical operation, data manipulation, or data load operation was zero. 4.1.5.5 carry/borrow bit (c-bit) the carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last arithmetic operation, logical operation, or data manipulation. the carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates. this bit is not set by an inc or dec instruction.
motorola section 4: cpu core page 28 mc68hc05v7 specification rev. 1.0
section 5: interrupts motorola page 29 mc68hc05v7 specification rev. 1.0 section 5 interrupts the mcu can be interrupted seven different ways: 1. nonmaskable software interrupt instruction (swi) 2. external asynchronous interrupt (irq ) 3. external interrupt via irq on pa0-pa7, pc0-pc7 4. internal 16-bit timer interrupt (timer) 5. internal serial peripheral interface interrupt (spi) 6. internal mdlc interrupt (mdlc) 7. internal 8-bit timer interrupt 5.1 cpu interrupt processing interrupts cause the processor to save register contents on the stack and to set the interrupt mask (i-bit) to prevent additional interrupts. unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. if interrupts are not masked (i-bit in the ccr is clear) and the corresponding interrupt enable bit is set the processor will proceed with interrupt processing. otherwise, the next instruction is fetched and executed. if an interrupt occurs the processor completes the current instruction, then stacks the current cpu register states, sets the i-bit to inhibit further interrupts, and finally checks the pending hardware interrupts. if more than one interrupt is pending following the stacking operation, the interrupt with the highest vector location shown in table 5-1 will be serviced first. the swi is executed the same as any other instruction, regardless of the i-bit state. when an interrupt is to be processed the cpu fetches the address of the appropriate interrupt software service routine from the vector table at locations $3ff2 thru $3fff as defined in table 5-1. table 5-1: vector address for interrupts and reset register n/a n/a n/a tsr msr spsr ctcsr flag name n/a n/a n/a ocf,icf,tof txms,rxms spif tofe,rtie interrupts reset software external interrupts ** 16-bit timer interrupts mdlc interrupt spi interrupt 8 bit timer interrupts cpu interrupt reset swi irq timer mdlc spi timer,rti vector address $3ffe-$3fff $3ffc-$3ffd $3ffa-$3ffb $3ff8-$3ff9 $3ff6-$3ff7 $3ff4-$3ff5 $3ff2-$3ff3 ** external interrupts include irq, porta and portc sources
motorola section 5: interrupts page 30 mc68hc05v7 specification rev. 1.0 the m68hc05 cpu does not support interruptible instructions, therefore, the maximum latency to the first instruction of the interrupt service routine must include the longest instruction execution time plus stacking overhead. latency = (longest instruction execution time + 10) x t cyc secs an rti instruction is used to signify when the interrupt software service routine is completed. the rti instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. figure 5-1 shows the sequence of events that occur during interrupt processing.
section 5: interrupts motorola page 31 mc68hc05v7 specification rev. 1.0 figure 5-1: interrupt processing flowchart n restore registers from stack: ccr, a, x, pc irq external interrupt load pc from appropriate vector set i bit in cc register stack pc, x, a, ccr clear irq request latch fetch next instruction execute instruction n n y y y n i-bit in ccr set? internal spi interrupt swi instruction ? n y rti instruction ? y from reset n y internal 16 bit timer interrupt n y internal mdlc interrupt n y internal 8 bit timer interrupt
motorola section 5: interrupts page 32 mc68hc05v7 specification rev. 1.0 5.2 reset interrupt sequence the reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner, as shown in figure 5-1. a low level input on the reset pin or internally generated rst signal causes the program to vector to its starting address which is specified by the contents of memory locations $3ffe and $3fff. the i-bit in the condition code register is also set. the mcu is configured to a known state during this type of reset as described in section 6 resets. 5.3 software interrupt (swi) the swi is an executable instruction and a non-maskable interrupt since it is executed regardless of the state of the i-bit in the ccr. if the i-bit is zero (interrupts enabled), the swi instruction executes after interrupts that were pending before the swi was fetched, or before interrupts generated after the swi was fetched. the interrupt service routine address is specified by the contents of memory locations $3ffc and $3ffd. 5.4 hardware interrupts all hardware interrupts except reset are maskable by the i-bit in the ccr. if the i-bit is set, all hardware interrupts (internal and external) are disabled. clearing the i-bit enables the hardware interrupts. there are two types of hardware interrupts which are explained in the following sections. 5.5 external interrupt (irq) the irq pin provides an asynchronous interrupt to the cpu. a block diagram of the irq function is shown in figure 5-2. note: the bih and bil instructions will only apply to the level on the irq pin itself, and not to the output of the logic or function with the port a and port c irq interrupts. the state of the individual port a and port c pins can be checked by reading the appropriate port a and port c pins as inputs.
section 5: interrupts motorola page 33 mc68hc05v7 specification rev. 1.0 figure 5-2: irq function block diagram the irq pin is one source of an external interrupt. all port a pins (pa0 thru pa7) and/or all port c pins (pc0 thru pc7) act as other external interrupt sources. these sources each have their own interrupt latch but are all combined into a single external interrupt request. the port a and port c interrupt sources are negative (falling) edge sensitive only . note that all port a pins and all port c pins are anded together, if con?ured as an input, to form the negative edge signal which sets the corresponding ?g bits. a high to low transition on any port a or port c pin con?ured as an input will therefore set the respective ?g bit. if a port a or port c pin is an input and is not used as a switch input in the system, it must remain high to prevent spurious interrupts from occurring. refer to 9.1.3 port a/c i/o pin interrupts for more detail on port a/port c interrupts. the irq pin interrupt source may be selected to be either edge sensitive or edge and level sensitive through a mask option or an mor bit. if the edge sensitive interrupt option is selected for the irq pin, only the irq latch r v d irq pin irqe level (mask option) irqf to irq processing in cpu irqa to bih & bil instruction sensing rst pa0 pa7 v d irqpa latch r irqpae r irqpce irqpaf irqpcf irq vector fetch v d v d v d v d irqpc latch ddra0 ddra7 pc0 pc7 ddrc0 ddrc7
motorola section 5: interrupts page 34 mc68hc05v7 specification rev. 1.0 irq latch output can activate an irqf ?g which creates an interrupt request to the cpu to generate the external interrupt sequence. when edge sensitivity is selected for the irq interrupt, it is sensitive to the following cases: falling edge on the irq pin. falling edge on any port a or port c pin with irq enabled. if the level option selected, the active low state of the irq pin can also activate an irqf flag, which creates an irq request to the cpu to generate the irq interrupt sequence. when edge and level sensitivity is selected for the irq interrupt, it is sensitive to the following cases: low level on the irq pin. falling edge on the irq pin. falling edge on any port a or port c pin with irq enabled. the irqe enable bit controls whether an active irqf flag (irq pin interrupt) can generate an irq interrupt sequence. the irqpae enable bit controls whether an active irqpaf flag (port a interrupt) can generate an irq interrupt sequence. the irqpce enable bit controls whether an active irqpcf flag (port c interrupt) can generate an irq interrupt sequence. the irq interrupt is serviced by the interrupt service routine located at the address specified by the contents of $3ffa and $3ffb. the irqf latch is automatically cleared by entering the interrupt service routine to maintain compatibility with existing m6805 interrupt servicing protocol. to allow the user to identify the source of the interrupt, the port interrupt flags (irqpaf and irqpcf) are not cleared automatically. these flags must be cleared within the interrupt handler prior to exit in order to prevent repeated re-entry. this is achieved by writing a logic one to the irqa (irq acknowledge) bit, which will clear all pending irq interrupts (including a pending irq pin interrupt). the interrupt request flags (irqpaf and irqpcf) are read only and cannot be cleared by writing to them. the acknowledge flag always reads as a logic 0. together, these features permit the safe use of read-modify-write instructions (for example, bset, bclr) on the icsr. note: although read modify write instruction use is allowable on the icsr, shift operations should be avoided due to the possibility of inadvertently setting the irqa. 5.5.1 irq control/status register (icsr) $1f the irq interrupt function is controlled by the icsr located at $001f. all unused bits in the icsr will read as logic zeros. the irqf bit is cleared and irqe bit is set by reset.
section 5: interrupts motorola page 35 mc68hc05v7 specification rev. 1.0 . figure 5-3: irq status & control register 5.5.1.1 irqa - irq interrupt acknowledge the irqa acknowledge bit clears an irq interrupt by clearing the irq, irqpa and irqpc latches. this is achieved by writing a logic one to the irqa acknowledge bit. writing a logic zero to the irqa acknowledge bit will have no effect on the any of the irq latches. if either the irq, irqpa or irqpc latch is not cleared within the irq service routine the cpu will re-enter the irq interrupt sequence continuously until the irq latches are all cleared. the irqa is useful for cancelling unwanted or spurious interrupts which may have occurred while servicing the initial irq interrupt. the irqa acknowledge bit will always read as a logic zero. the irqa function is activated by reset. note: the irq latch is cleared automatically during the irq vector fetch. the irqpa and irqpc latches are not cleared automatically (to permit interrupt source differentiation) and must be cleared from within the irq service routine. 5.5.1.2 irqpcf - port c irq interrupt request the irqpcf flag bit indicates that a port c irq request is pending. writing to the irqpcf flag bit will have no effect on it. the irqpcf flag bit must be cleared by writing a logic one to the irqa acknowledge bit. in this way an additional irqpcf flag bit that is set while in the service routine can be ignored by clearing the irqpcf flag bit before exiting the service routine. if the additional irqpcf flag bit is not cleared in the irq service routine and the irqpce enable bit remains set, the cpu will re-enter the irq interrupt sequence continuously until either the irqpcf flag bit or the irqpce enable bit is clear. this bit is operational regardless of the state of the irqpce bit. the irqpcf bit is cleared by reset. 5.5.1.3 irqpaf - port a irq interrupt request the irqpaf flag bit indicates that a port a irq request is pending. writing to the irqpaf flag bit will have no effect on it. the irqpaf flag bit must be cleared by writing a logic one to the irqa acknowledge bit. in this way an additional irqpaf flag bit that is set while in the service routine can be ignored by clearing the irqpaf flag bit before exiting the service routine. if the additional irqpaf flag bit is not cleared in the irq service routine and the irqpae enable bit remains set, the cpu will re-enter the irq interrupt sequence continuously until either the irqpaf flag bit or the irqpae enable bit is clear. this bit is operational regardless of the state of the irqpae bit. the irqpaf bit is cleared by reset. icsr $001f 1 7 w r 0000000 reset t 6543210 irqe irqf 0 irqa 0 irqpaf irqpae irqpce irqpcf
motorola section 5: interrupts page 36 mc68hc05v7 specification rev. 1.0 5.5.1.4 irqf - irq interrupt request the irqf flag bit indicates that an irq request is pending. writing to the irqf flag bit will have no effect on it. the irqf flag bit is cleared when the irq vector is fetched prior to the service routine being entered. the irqf flag bit can also be cleared by writing a logic one to the irqa acknowledge bit to clear the irq latch. in this way any additional irqf flag bit that is set while in the service routine can be ignored by clearing the irqf flag bit before exiting the service routine. if the additional irqf flag bit is not cleared in the irq service routine and the irqe enable bit remains set, the cpu will re-enter the irq interrupt sequence continuously until either the irqf flag bit or the irqe enable bit is clear. the irq latch is cleared by reset. this flag can be set only when the irqe enable is set. 5.5.1.5 irqpce - port c irq interrupt enable the irqpce bit controls whether the irqpcf flag bit can or cannot initiate an irq interrupt sequence. if the irqpce enable bit is set the irqpcf flag bit can generate an interrupt sequence. if the irqpce enable bit is cleared the irqpcf flag bit cannot generate an interrupt sequence. reset clears the irqpce enable bit, thereby disabling port c irq interrupts. in addition, reset also sets the i-bit, which masks all interrupt sources. execution of the stop or wait instructions does not effect the irqpce bit. 5.5.1.6 irqpae - port a irq interrupt enable the irqpae bit controls whether the irqpaf flag bit can or cannot initiate an irq interrupt sequence. if the irqpae enable bit is set the irqpaf flag bit can generate an interrupt sequence. if the irqpae enable bit is cleared the irqpaf flag bit cannot generate an interrupt sequence. reset clears the irqpae enable bit, thereby disabling port a irq interrupts. in addition, reset also sets the i-bit, which masks all interrupt sources. execution of the stop or wait instructions does not effect the irqpae bit. note: the irqpae and irqpce mask bits must be set prior to entering stop or wait modes if port irq interrupts are to be enabled. 5.5.1.7 irqe - irq interrupt enable the irqe bit controls whether the irqf flag bit can or cannot initiate an irq interrupt sequence. if the irqe enable bit is set the irqf flag bit can generate an interrupt sequence. if the irqe enable bit is cleared the irqf flag bit cannot bet set and therefor cannot generate an interrupt sequence. reset sets the irqe enable bit, thereby enabling irq interrupts once the i-bit is cleared. execution of the stop or wait instructions causes the irqe bit to be set in order to allow the external irq to exit these modes. in addition, reset also sets the i-bit, which masks all interrupt sources. 5.5.2 external interrupt timing if the interrupt mask bit (i bit) of the ccr is set, all maskable interrupts (internal and external) are disabled. clearing the i bit enables interrupts. the interrupt request is latched immediately following the falling edge of the irq source. it is then synchronized internally
section 5: interrupts motorola page 37 mc68hc05v7 specification rev. 1.0 and serviced as specified by the contents of $3ffa and $3ffb.the irq timing diagram is shown in figure 5-4. figure 5-4: external interrupts timing diagram either a level-sensitive and edge-sensitive trigger, or an edge-sensitive-only trigger is available as a mask option for the irq pin only. 5.6 16 bit timer interrupt there are three different timer interrupt flags that cause a timer interrupt whenever they are set and enabled. the interrupt flags are in the timer status register (tsr), and the enable bits are in the timer control register (tcr). any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory location $3ff8 and $3ff9. 5.7 mdlc interrupt the mdlc transmit message successful and receive message successful interrupts are respectively generated by the txms and rxms bits of the mdlc status register (msr). in addition a wake-up from stop or wait mode can also generate an interrupt from the mdlc. the mdlc interrupt enable (ie) bit is located in the mdlc control register (mcr). provided the ie bit is set (and the ccr i bit is clear), all interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory location $3ff6 and $3ff7. 5.8 spi interrupt there are two different spi interrupt flags that cause an spi interrupt whenever they are set and enabled. the interrupt flags are in the spi status register (spsr), and the enable bits are in the spi control register (spcr). either of these interrupts will vector to the irq t ilih t ilil t ilih irq 1 (port) irq n (port) irq (mcu) . . .
motorola section 5: interrupts page 38 mc68hc05v7 specification rev. 1.0 same interrupt service routine, located at the address specified by the contents of memory locations $3ff4 and $3ff5. 5.9 8-bit timer interrupt this timer can create two types of interrupts. a timer overflow interrupt will occur whenever the 8 bit timer rolls over from $ff to $00 and the enable bit tofe is set. a real time interrupt will occur whenever the programmed time elapses and the enable bit rtie is set. see section 12 core timer. this interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations $3ff2 and $3ff3.
section 6: resets motorola page 39 mc68hc05v7 specification rev. 1.0 section 6 resets the mcu can be reset from six sources: one external input and five internal restart conditions. the reset pin is an input with a schmitt trigger as shown in figure 6-1. all the internal peripheral modules will be reset by the internal reset signal (rst). refer to figure 6-2 for reset timing detail. figure 6-1: reset block diagram 6.1 external reset (reset ) the reset pin is the only external source of a reset. this pin is connected to a schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. this external reset occurs whenever the reset pin is pulled below the lower threshold and remains in reset until the reset pin rises above the upper threshold. this active low input will generate the rst signal and reset the cpu and peripherals. termination of the external reset input or the internal cop watchdog reset are the only reset sources that can alter the operating mode of the mcu. note: activation of the rst signal is generally referred to as reset of the device, unless otherwise specified. cpu latch reset cop watchdog (copr) rst osc data address ph2 to other peripherals s low-voltage reset (lvr) v dd irq /v tst mode select to irq logic latch r power-on reset (por) v dd illegal address (illaddr) address ph2 clocked one-shot (pulse width = 3 x e-clk) d d disabled stop instruction stopen
motorola section 6: resets page 40 mc68hc05v7 specification rev. 1.0 the reset pin can also act as an open drain output. it will be pulled to a low state by an internal pulldown that is activated by any reset source. this reset pulldown device will only be asserted for 3-4 cycles of the internal clock, ph2 (ph2 period = e clock period) or as long as an internal reset source is asserted. when the external reset pin is asserted, the pulldown device will be turned on for only the 3-4 internal clock cycles. 6.2 internal resets the five internally generated resets are the initial power-on reset function, the cop watchdog timer reset, the illegal address detector, the low-voltage reset, and the disabled stop instruction. termination of the external reset input or the internal cop watchdog timer are the only reset sources that can alter the operating mode of the mcu. the other internal resets will not have any effect on the mode of operation when their reset state ends. all internal resets will also assert (pull to logic zero) the external reset pin for the duration of the reset or 3-4 internal clock cycles, whichever is longer. 6.2.1 power-on reset (por) the internal por is generated on power-up to allow the clock oscillator to stabilize. the por is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). there is an oscillator stabilization delay of 4064 internal processor bus clock cycles (ph2) after the oscillator becomes active. the por will generate the rst signal which will reset the cpu. if any other reset function is active at the end of this 4064 cycle delay, the rst signal will remain in the reset condition until the other reset condition(s) end. por will activate the reset pin pulldown device connected to the pin. v dd must drop below v por in order for the internal por circuit to detect the next rise of v dd . 6.2.2 operation in stop and wait if enabled, the lvr supply voltage sense option is active during stop and wait. any reset source can bring the mcu out of stop or wait modes.
section 6: resets motorola page 41 mc68hc05v7 specification rev. 1.0 figure 6-2: reset and por timing diagram pch pcl osc1 2 reset internal processor internal address bus 1 3ffe 3fff v dd 4064 t cyc t cyc t rl internal data bus 1 3ffe 3ffe 3ffe 3ffe new pc 3fff notes: 1. internal timing signal and bus information not available externally. 2. osc1 line is not meant to represent frequency. it is only used to represent time. 3. the next rising edge of the internal processor clock following the rising edge of reset initiates the reset sequence. 4. v dd must fall to a level lower than v por in order to recognized as a power on reset. 3 new new op code pcl pch new pc new pc op code new pc clock 1 0v < v por 4
motorola section 6: resets page 42 mc68hc05v7 specification rev. 1.0 6.2.3 computer operating properly reset (copr) the mcu contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. if the cop watchdog timer is allowed to time- out, an internal reset is generated to reset the mcu. regardless of an internal or external reset, the mcu comes out of a cop reset according to the standard rules of mode selection. the cop reset function is enabled or disabled by a mask option and is verified during production testing. the cop watchdog reset will activate the internal pulldown device connected to the reset pin. 6.2.3.1 resetting the cop preventing a cop reset is done by writing a ??to the copf bit. this action will reset the counter and begin the time-out period again. the copf bit is bit 0 of address $3ff0. a read of address $3ff0 will return user data programmed at that location. 6.2.3.2 cop during wait mode the cop will continue to operate normally during wait mode. the software should pull the device out of wait mode periodically and reset the cop by writing to the copf bit to prevent a cop reset. 6.2.3.3 cop during stop mode when the stop enable mask option is selected, stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. the cop counter will be reset when stop mode is entered. if a reset is used to exit stop mode, the cop counter will be held in reset during the 4064 cycles of start up delay. if any operable interrupt is used to exit stop mode, the cop counter will not be reset during the 4064 cycle start up delay and will have that many cycles already counted when control is returned to the program. 6.2.3.4 cop watchdog timer considerations the cop watchdog timer is active in all modes of operation if enabled by a mask option. if the cop watchdog timer is selected by a mask option, any execution of the stop instruction (either intentional or inadvertent due to the cpu being disturbed) will cause the oscillator to halt and prevent the cop watchdog timer from timing out. therefore, it is recommended that the stop instruction should be disabled if the cop watchdog timer is enabled. if the cop watchdog timer is selected by a mask option, the cop will reset the mcu when it times out. therefore, it is recommended that the cop watchdog should be disabled for a system that must have intentional uses of the wait mode for periods longer than the cop time-out period. the recommended interactions and considerations for the cop watchdog timer, stop instruction, and wait instruction are summarized in table 6-1.
section 6: resets motorola page 43 mc68hc05v7 specification rev. 1.0 table 6-1: cop watchdog timer recommendations 6.2.3.5 cop register the cop register is shared with the msb of an unimplemented user interrupt vector as shown in figure 6-3. reading this location will return whatever user data has been programmed at this location. writing a ??to the copr bit in this location will clear the cop watchdog timer. figure 6-3: cop watchdog timer location 6.2.4 low-voltage reset (lvr) the internal low voltage (lvr) reset is generated when v dd falls below the lvr threshold v lvri and will be released following a por delay starting when v dd rises above v lvrr . the lvr threshold is tested to be above the minimum operating voltage of the microcontroller and is intended to ensure that the cpu will be held in reset when the v batt supply voltage is below reasonable operating limits. however, it should be noted that the lvr monitors v dd not v batt . a mask option is provided to disable the lvr when the device is expected to normally operate at low voltages. note that the v dd rise and fall slew rates (s vddr and s vddf ) must be within the specification for proper lvr operation. if the specification is not met, the circuit will operate properly following a delay of v dd /slew rate. the lvr will generate the rst signal that will reset the cpu and other peripherals. as it is not possible to determine the level of the internal v dd at the point v batt recovers (and por is not intended to detect a loss of v dd ), an lvr will always recover using a por delay. the low voltage reset will activate the internal pulldown device connected to the reset pin. wait time less than cop time-out stop instruction wait time then the cop watchdog timer should be as follows: disable cop by mask option converted to reset enable or disable cop by mask option wait time more than cop time-out any length wait time acts as stop disable cop by mask option converted to reset if the following conditions exist: unimplemented vector & cop watchdog timer x $3ff0 w r copr unimplemented read write addr 1 0 2 3 4 5 6 7 register x x x x x x x
motorola section 6: resets page 44 mc68hc05v7 specification rev. 1.0 if any other reset function is active at the end of the lvr reset signal, the rst signal will remain in the reset condition until the other reset condition(s) end. 6.2.5 illegal address an illegal address reset is generated when the cpu attempts to fetch an instruction from either unimplemented address space ($01c0 to $023f and $02c0 to $17ff) or i/o address space ($0000 to $003f). the illegal address reset will activate the internal pulldown device connected to the reset pin. 6.2.6 disabled stop instruction when the mask option is selected to disable the stop instruction, execution of a stop instruction results in an internal reset. this activates the internal pulldown device connected to the reset pin.
section 7: power supply and regulation motorola page 45 mc68hc05v7 specification rev. 1.0 section 7 power supply and regulation the mc68hc05v7 contains a low-power cmos on-chip fixed voltage regulator to provide internal power to the mcu from an external dc source. the mcu features separate analog and digital power and ground pins to help decrease common-mode noise contamination of the analog subsystems. the supply pins are also grouped in adjacent pairs to permit optimal decoupling and to minimize radiated rf emissions. 7.1 internal power supply the on-chip voltage regulation and power supply control circuitry is comprised of four elements: the primary regulator, the secondary regulator, the power mode control, and the lvr circuitry. the primary internal regulator can be disabled through register control bits. when it is desired to use an external voltage regulator, regulated power must be provided to both sets of v dd /vss pins. when the primary regulator is disabled, the regulator input pin (v batt ) is still used to power the mdlc? physical interface. 7.1.1 primary 5v regulator the primary 5v regulator accepts a regulated input supply and provides a regulated 5v supply to all the digital sections of the device with the exception of the v ign and power supply control logic. the output of this regulator is also connected to the v dd pins to allow for decoupling of the digital supply pins (v dd ), to supply a decoupled and/or filtered supply to the analog supply pin (v cca ) and to provide an external power source for off chip usage. the regulator requires an external 10 uf capacitor for stability. see figure 7-6 : mc68hc05v7 on-chip power supply configuration for the most suitable supply pin and external capacitor connections. the primary regulator can be disabled through software by clearing the pdc bit of the miscellaneous register (see figure 7-1). once disabled, the regulator can only be enabled by a rising edge on the v ign or bus (if mask option enabled) pins. when disabled, the primary regulator output will be connected to v ss if the v ddc mask option has been selected. this prevents unintentional device operation using current sourced through external pullup components. any loss of v batt sufficient to trigger an lvr will cause the device to be reset. the device will remain in the reset state for the duration of the lvr condition or until the internal v dd drops below the functional level of the device, at which point reset no longer has meaning. if the drop in v batt that triggers an lvr is transient, the internal rst will be asserted for a minimum 4064 cycles of the cpu bus clock, ph2 (the por delay). 7.1.2 secondary regulator the secondary regulator provides an independent supply to the small amount of power supply control logic required to provide some of the power moding functions. the
motorola section 7: power supply and regulation page 46 mc68hc05v7 specification rev. 1.0 secondary regulator is always enabled (regardless of the mask option selection) but consumes significantly less power than the primary regulator. the secondary regulator will provide sufficient voltage to the control logic provided v batt remains above the minimum voltage. 7.2 miscellaneous register the software power supply management functions are performed through the miscellaneous register located at $002f. although the oce bit of the miscellaneous register is unrelated to the power supply, it will be described here. figure 7-1: miscellaneous register 7.2.1 igns - ignition status bit this is a read only status bit which indicates the state of the v ign pin. 0 - the v ign pin is less than the v il level for this pin. 1 - the v ign pin is greater than the v ih level for this pin. warning: there is not hysteresis or hardware debounce on the v ign pin and hence, in the state of this bit. this bit cannot be read unless the regulator option is enabled. see 17.3 dc electrical characteristics for v ih and v il levels. 7.2.2 oce - output compare enable this bit controls the function of the pb6 pin. 0 - pb6 functions as a normal i/o pin. 1 - pb6 becomes the tcmp output pin for the 16-bit timer. see section 11 16-bit timer for a description of the tcmp function. reset clears this bit. 7.2.3 pdc - power down control this bit controls the internal primary voltage regulator. 0 - disables the internal primary voltage regulator. 1 - enables the internal primary voltage regulator. igns miscellaneous register $002f w r pdc unimplemented read write addr 1 0 2 3 4 5 6 7 register 0 oce 0 0 0 -0------ reset t 0
section 7: power supply and regulation motorola page 47 mc68hc05v7 specification rev. 1.0 this bit has no affect unless the regulator option is set. this bit is not affected by reset and must be initialized by software. 7.3 power moding a flow diagram depicting all conditions that the mcu could enter is shown in figure 7-2. the chip can be operated in one of three distinct power modes. the first mode is "power off". in this mode, the chip is not being powered from any source. the v batt pin voltage is below that required by the regulator circuit to provide an output voltage that is within regulation limits. the second mode is "standby power". in this mode, the v batt voltage is above the required minimum, but the user has not turned the primary regulator on. the secondary regulator and the power mode logic are powered up. standby mode can be exited by either reducing the v batt voltage or by turning the primary regulator on. the third mode is "power up" mode. in this mode, the cpu and peripherals can perform their normal processing tasks. the only way to exit from this mode is to lose regulator output power. losing regulator output power can happen in one of three ways: 1) the v batt voltage can fall below the required minimum level causing v dd to fall below minimum, 2) software can turn the primary regulator off, and 3) some sort of fault on the external v dd pin. in any case, the lvr reset will be asserted to protect the system as the v dd voltage is falling. transitioning between these states is referred to as power moding.
motorola section 7: power supply and regulation page 48 mc68hc05v7 specification rev. 1.0 figure 7-2: mc68hc05v7 power moding flow diagram power off mode standby power mode v ign por delay primary reg. power up mode v dd >min primary reg. lvr steady state condition decision transition bus enabled pdc=0 disabled (chip reset) v batt >min no yes no yes no yes no yes or
section 7: power supply and regulation motorola page 49 mc68hc05v7 specification rev. 1.0 7.4 regulator control logic the ignition state monitor pin, v ign , or the mdlc bus pin (provided the mdlcpu mask option is selected) allows the user to wake-up the primary power supply and subsequently the mcu. a positive transition applied to either pin will enable the primary regulator. the state of the v ign pin can be determined by reading the igns bit of the miscellaneous register. the primary regulator can be disabled by clearing the pdc bit in the miscellaneous register. the bus or v ign pin need not be low to write the pdc bit. once the regulator has been disabled, a rising edge on v ign or bus will re-enable the regulator. to ensure the validity of the pdc bit during a v dd transition, the pdc bit is always copied into a latch powered by the secondary regulator. the bit is copied during a write to the miscellaneous register. when the regulator is powered up by a rising edge of bus or v ign , the latch that contains the copy of the pdc bit will be initialized to a 1 and may have a different value than the pdc bit itself. software should always initialize the pdc bit to a 1. the latch will be set on the rising edge of v ign or bus. this will give the primary regulator, cpu, and software ample time to start up and initialize the pdc bit to a 1. at this point, the mcu will transition to the power up mode. (see figure 7-2.) in order to ensure that the primary regulator starts up when v batt voltage is applied to the mcu, a low to high transition should be provided on the v ign pin once v batt reaches minimum level, shown in figure 7-3. figure 7-3: regulator startup note: once enabled, the regulator can only be disabled through software. voltage time min v batt <= 0.4*v batt v batt v ign v ign >min v batt
motorola section 7: power supply and regulation page 50 mc68hc05v7 specification rev. 1.0 note: if the lvr option is enabled, reset will be asserted when v dd drops to the appropriate level. note: before the pdc bit is written to a 0, the state of the igns bit should be debounced in software. this will ensure that the primary regulator does not power up with any bounce that may be present on vign. 7.4.1 mask options the regulator has three mask options associated with it. the first one is the mdlcpu option. if this option is enabled, a rising edge on the mdlc bus pin or the v ign pin can bring the primary regulator out of the standby power mode. if this option is not enabled, only the v ign pin will bring the primary regulator out of the standby power mode. the second mask option is the v ddc option. this option, if enabled, will enable an active pulldown device, connected between v dd and v ss , to turn on when the primary regulator is disabled. this option should not be selected if an external voltage regulator is being used. the third mask option is the regulator enable option. if it is not desired to use the on-board voltage regulator, this option should not be selected. in this case the secondary regulator will still remain active in order to properly keep the primary regulator turned off. while the regulator is not enabled the mdlcpu option will remain operational but will serve no purpose. the v ddc option and the miscellaneous register will continue to operate normally. the v ddc function (v dd to v ss clamping device) uses the pdc bit to determine when to turn the clamping device on. if this option is enabled and the pdc bit is written to a "0", the clamping device will turn on. it will not turn off until a rising edge is detected on v ign or a rising edge on the bus pin is detected provided the mdlcpu option is selected. if the configuration shown in figure 7-4 is used with the regulator enable option selected, the mdlcpu and v ddc options may be selected. in addition, software must write a ??to the pdc bit in the miscellaneous register to initialize it after power-up. this prevents read- modify-write instructions to the miscellaneous register from accidentally clearing the pdc bit.
section 7: power supply and regulation motorola page 51 mc68hc05v7 specification rev. 1.0 figure 7-4: using the 68hc05v7 with an external regulator if the regulator enable option is not selected, the mdlcpu option and the pdc bit have no affect. the v ddc option will remain available. figure 7-5 is a block diagram of the regulator control circuit. it illustrates how the miscellaneous register bits, v ign , bus and the mask options interact in the power moding scheme. v batt v dd v dd v cca v ign v ss ,v ss v ssa1 v ssa2 v batt external regulator +5 volts 0.1 m 0.1 m 0.1 m mcu 705v8
motorola section 7: power supply and regulation page 52 mc68hc05v7 specification rev. 1.0 figure 7-5: power moding block diagram primary regulator v batt v dd secondary regulator misc. reg. pdc igns ... latch d q latch d q bus v ign v batt v ee (vee) enable q q s r latch d q s latch d q v ee r c v ddc mask option mdlc pu mask option
section 7: power supply and regulation motorola page 53 mc68hc05v7 specification rev. 1.0 7.5 power supply configuration the recommended decoupling and interconnection of the various power supply pins is shown in figure 7-6. note that this diagram does not reflect actual pin location or order. figure 7-6: mc68hc05v7 on-chip power supply configuration 7.5.1 decoupling recommendations to provide effective decoupling and to reduce radiated rf emissions, the small decoupling capacitors must be located as close to the supply pins as possible. the self-inductance of these capacitors and the parasitic inductance and capacitance of the interconnecting traces determines the self-resonant frequency of the decoupling network. too low a frequency will reduce decoupling effectiveness and could increase radiated rf emissions from the system. a low value capacitor (470 pf to 0.01 uf) placed in parallel with the other capacitors will improve the bandwidth and effectiveness of the network. primary internal (digital) v batt v dd v ss v dd 0.1uf 0.1uf 10 uf v ssa1 v ssa2 v cca a/d converter mdlc analog 0.1uf 0.1uf single point ground >= min v batt v ign 5v regulator v ign logic enable secondary regulator v ign supply eprom v dd and v cc required for regulator stability note: the 10 uf capacitor should be placed on the v dd pin closest to the v ign pin. ignition v batt c* r* * rc values should be chosen to provide a v ign voltage of <= 0.4*v batt once v batt reaches minimum level. v ss
motorola section 7: power supply and regulation page 54 mc68hc05v7 specification rev. 1.0 figure 7-7: hc705v8 internal power routing 1) v dd to v ssd (pins 30 & 31): on-chip regulator output decoupling. as with any reg- ulator, the output must be adequately decoupled to maintain stability of the regulator. decouple with at least 10 uf tantalum or aluminum electrolytic bulk in parallel with 0.1uf ceramic or polystyrene capacitor for high frequency (hf) stability. locate both capacitors as close as possible to the v dd and v ssd pins, ensuring the hf capacitor is closest. the two v ssd pins should be externally connected together. rext2 rext1 v ign v dd v ssd pd0/an0 pe0/an8 pe1/an9 pe2/an10 pe3/an11 pd1/an1 pd2/an2 v refh v cca v ssa1 v refl n.c. n.c . irq rst osc1 osc2 v dd v ssd pwm pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 n.c. pf3/miso pf2/mosi pf1/sclk pf0/ss pb0 pb1 pb2 pb3 pb4 pb5 pb6/tcmp pb7/tcap v ssa2 load bus v pp n.c. pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pe7/an pe6/an pe5/an pe4/an pd7/an pd6/an pd5/an pd4/an pd3/an regulator dlc a/d r r ~ 40 ohns digital logic blocks 68-pin plcc package shown 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
section 7: power supply and regulation motorola page 55 mc68hc05v7 specification rev. 1.0 the effect of not connecting the two v dd pins together is under evaluation and it is recom- mended that they be connected at this time. 2) v dd to v ssd (pins 3 & 4): mcu internal digital power decoupling. these pins are connected to the on-chip regulator output via a small resistance. decouple with a 0.1uf ceramic or polystyrene capacitator. if the self-resonance frequency of the decoupling cir- cuit (assume 4nh per bond wire) is too low, add a 0.01uf or smaller capacitor in parallel to increase the bandwidth of the decoupling network. ensure the smaller capacitor is located closest to the v dd and v ssd pins. 3) v cca to v ssa1 and v ssa2 : analog subsystem power supply pins. these pins are internally isolated from the digital v dd and v ss supplies. the v ssa1 pin provides a ground return for the a/d subsystem. the v ssa2 pin provides a ground return for the dlc sub- system. the analog supply pins should be appropriately ?tered to prevent any external noise effecting the analog subsystems. the v ssa1 and v ssa2 pins should be brought together with the digital ground at a single point which has a low (hf) impedance to ground to prevent common mode noise problems. if this is not practical, then the v ssa1 and v ssa2 printed circuit board (pcb) traces should be routed in such a manner that digi- tal ground return current is impeded from passing through the analog input ground refer- ence as shown in the single sided pcb example below . v ssd v7 v ssa anx to system gnd ain v ssd v7 v ssa anx agnd ain gnd shielded cable, gnd shielded cable, twisted pair, etc. poor analog grounding better analog grounding twisted pair, etc.
motorola section 7: power supply and regulation page 56 mc68hc05v7 specification rev. 1.0
section 8: low-power modes motorola page 57 mc68hc05v7 specification rev. 1.0 section 8 low-power modes the mc68hc05v7 is capable of running in one of several low-power operational modes. the wait and stop instructions provide two modes that reduce the power required for the mcu by stopping various internal clocks and/or the on-chip oscillator. the stop and wait instructions are not normally used if the cop watchdog timer is enabled. a mask option is provided to convert the stop instruction to an internal reset. the flow of the stop and wait modes is shown in figure 8-2. 8.1 stop instruction the stop instruction can result in one of two operations depending on the mask options. if the stop option is enabled, the stop instruction operates like the stop in normal mc68hc05 family members and places the device in the low power stop mode. if the stop option is disabled, the stop instruction will cause a chip reset when executed. 8.1.1 stop mode execution of the stop instruction, with the proper mask option, places the mcu in its lowest power consumption mode. in the stop mode the internal oscillator is turned off, halting all internal processing, including the cop watchdog timer. during the stop mode, the tcr bits are altered to remove any pending timer interrupt request and to disable any further timer interrupts. the timer prescaler is cleared. the i bit in the ccr is cleared and the irqe mask is set in the icsr to enable external interrupts. all other registers and memory remain unaltered. all input/output lines remain unchanged. the processor can be brought out of the stop mode only by an external interrupt or reset. the mcu can be brought out of the stop mode by only one of the following: irq pin external interrupt externally or internally generated reset falling edge on any port a or port c pin (if enabled) rising edge on the mdlc bus pin when exiting the stop mode, the internal oscillator will resume after a 4064 internal processor clock cycle oscillator stabilization delay, as shown in figure 8-1. note: execution of the stop instruction with the proper mask option will cause the oscillator to stop and therefore disable the cop watchdog timer. if the cop watchdog timer is to be used, the stop mode should be disabled by selecting the proper mask option. see 6.2.3.4 cop watchdog timer considerations for more details.
motorola section 8: low-power modes page 58 mc68hc05v7 specification rev. 1.0 figure 8-1: stop recovery timing diagram 3ffe 3ffe 3ffe 3ffe 3fff internal address bus internal clock irq 3 irq 2 reset osc1 1 t ilch 4064 t cyc reset or interrupt vector fetch t lih t rl notes: 1. represents the internal gating of the osc1 pin. 2. irq pin edge-sensitive mask option or port a/c pin. 3. irq pin level and edge sensitive mask option. mdlc bus idle
section 8: low-power modes motorola page 59 mc68hc05v7 specification rev. 1.0 figure 8-2: stop/wait flowcharts 8.1.2 wait instruction the wait instruction places the mcu in a low-power mode, which consumes more power than the stop mode. in the wait mode the internal processor clock is halted, suspending all processor and internal bus activity. internal timer clocks remain active, permitting interrupts to be generated from the timer or a reset to be generated from the cop watchdog timer. execution of the wait instruction automatically clears the i-bit in the condition code register. all other registers, memory, and input/output lines remain in their previous states. mdlc bus edge? y n 1. fetch reset vector or 2. service interrupt a. stack b. set i-bit c. vector to interrupt routine wait stop mask option en- abled? y n external reset ? y n irq external interrupt? y n stop external oscillator, stop internal timer clock, and reset startup delay restart external oscillator, and stabilization delay stop internal processor clock, clear i-bit in ccr, end of startup delay y n irq external interrupt? y n external oscillator active, and internal timer clock active restart internal processor clock stop internal processor clock, clear i-bit in ccr, timer internal interrupt? y n external reset ? y n stop mdlc bus edge? y n port a or c falling edge? y n port a or c falling edge? y n reset chip
motorola section 8: low-power modes page 60 mc68hc05v7 specification rev. 1.0 if timer interrupts are enabled, a timer interrupt will cause the processor to exit the wait mode and resume normal operation. the timer may be used to generate a periodic exit from the wait mode. the mcu can be brought out of the wait mode by one of the following: timer interrupt from either timer irq pin external interrupt externally or internally generated reset falling edge on any port a or port c pin (if enabled) rising edge on the mdlc bus pin
section 9: parallel i/o motorola page 61 mc68hc05v7 specification rev. 1.0 section 9 pa rallel i/o in the single-chip mode there are 28 bidirectional i/o lines arranged as three 8-bit i/o ports (ports a, b and c) and one 4-bit i/o port (port f), and 16 input only lines arranged as two 8-bit ports (ports d and e). the individual bits in the i/o ports are programmable as either inputs or outputs under software control by the data direction registers (ddrs). the port a and port c pins also have the additional properties of acting as additional irq interrupt input sources. 9.1 port a and port c port a and port c are 8-bit bidirectional ports which share all of their pins with the irq interrupt system as shown in figure 9-1. each pin is controlled by the corresponding bits in a data direction register and a data register. the port a data register is located at address $0000.the port c data register is located at address $0002. the port a data direction register (ddra) is located at address $0004. the port c data direction register (ddrc) is located at address $0006. reset clears ddra and ddrc. the data registers are unaffected by reset. figure 9-1: port a and port c i/o circuitry 9.1.1 port a/c data registers each port a/c i/o pin has a corresponding bit in the port a/c data register. when a port a/c pin is programmed as an output the state of the corresponding data register bit determines the state of the output pin. when a port a/c pin is programmed as an input, any to irq interrupt system port a/c bits 0 thru 7 read $0000/02 write $0000/02 read $0004/06 data register bit i/o pin output internal hc05 data bus reset (rst) write $0004/06 data direction register bit
motorola section 9: parallel i/o page 62 mc68hc05v7 specification rev. 1.0 read of the port a/c data register will return the logic state of the corresponding i/o pin. the port a/c data register is unaffected by reset. 9.1.2 port a/c data direction register each port a/c i/o pin may be programmed as an input by clearing the corresponding bit in the ddra/c, or programmed as an output by setting the corresponding bit in the ddra/c. the ddra can be accessed at address $0004. the ddrc can be accessed at address $0006. the ddra and ddrc are cleared by reset. 9.1.3 port a/c i/o pin interrupts the inputs of all eight bits of port a and port c are anded into the irq input of the cpu. each port has its own interrupt request latch to enable the user to differentiate between the irq sources. the port irq inputs are falling edge sensitive only. any port a or port c pin can be disabled as an interrupt input by setting the corresponding ddr bit. any port a or port c pins that are outputs will not cause a port interrupt when the pin transitions from a 1 to a 0. however, since all inputs pins are anded together to form the interrupt signal, any input pin that remains low will inhibit the interrupt flag bit from being set when subsequent pins transition low. note: the bih and bil instructions will only apply to the level on the irq pin itself, and not to the internal irq input to the cpu. therefore bih and bil cannot be used to obtain the result of the logical combination of the eight pins of port a or port c. 9.2 port b port b is an 8-bit bidirectional port. each port b pin is controlled by the corresponding bits in a data direction register and a data register as shown in figure 9-2. pb6 and pb7 are shared with 16 bit timer functions. see section 11 16-bit timer. the port b data register is located at address $0001. the port b data direction register (ddrb) is located at address $0005. reset clears the ddrb register. the port b data register is unaffected by reset
section 9: parallel i/o motorola page 63 mc68hc05v7 specification rev. 1.0 . figure 9-2: port b i/o circuitry 9.2.1 port b data register each port b i/o pin has a corresponding bit in the port b data register. when a port b pin is programmed as an output the state of the corresponding data register bit determines the state of the output pin. when a port b pin is programmed as an input, any read of the port b data register will return the logic state of the corresponding i/o pin. the port b data register is unaffected by reset. pb7 serves as the tcap input and pb6 serves as the tcmp output if the oce bit in the misc register is set. see 7.2 miscellaneous register . 9.2.2 port b data direction register each port b i/o pin may be programmed as an input by clearing the corresponding bit in the ddrb, or programmed as an output by setting the corresponding bit in the ddrb. the ddrb can be accessed at address $0005. the ddrb is cleared by reset. 9.3 port d and port e port d is an 8-bit input only port that shares all of its pins with the a/d converter (an0 through an7) as shown in figure 1-6. the port d data register is located at address $0003. port e is an 8-bit input only port which also shares all of its pins with the a/d converter (an8 through an15). the port e data register is located at address $002b. when the a/d converter is active, one of these 16 input ports may be selected by the a/d multiplexer for conversion. a logical read of a selected input port will always return 0. note: port e is not bonded out in the 56-pin sdip packaged version. read $0001 write $0001 read $0005 data register bit i/o pin output internal hc05 data bus reset (rst) write $0005 data direction register bit
motorola section 9: parallel i/o page 64 mc68hc05v7 specification rev. 1.0 figure 9-3: port d and port e circuitry 9.4 port f port f is a 4-bit bidirectional port which shares all of its pins with the spi subsystem. if the spi is enabled, port f3-1 are disabled as regular i/o pins. pf0 can still function as an output if the ddr bit is set. each port f pin is controlled by the corresponding bits in a data direction register and a data register. the port f data register is located at address $002c. the port f data direction register (ddrf) is located at address $002e. reset clears the ddrf register. the port f data register is unaffected by reset. port f is shared with the spi. 9.4.1 port f data register each port f i/o pin has a corresponding bit in the port f data register. when a port f pin is programmed as an output the state of the corresponding data register bit determines the state of the output pin. when a port f pin is programmed as an input, any read of the port f data register will return the logic state of the corresponding i/o pin. the port f data register may be read even if the spi subsystem is enabled. the port f data register is unaffected by reset. 9.4.2 port f data direction register each port f i/o pin may be programmed as an input by clearing the corresponding bit in the ddrf, or programmed as an output by setting the corresponding bit in the ddrf. the ddrf can be accessed at address $002e. if the spi subsystem is enabled (spe bit is set), the ddrf bit corresponding to pf0 will determine the function of the pf0 pin. if ddrf0 is cleared, the pf0 pin functions as a ss (slave select) input to the spi. if ddrf0 is set, then pf0 can serve as a normal output pin. when the spi subsystem is enabled, the ddrf3-1 bits are set or cleared according to the required pin function. the ddrf is cleared by reset. read $0003/2b input pin internal hc05 data bus v ss to a/d sampling circuitry to a/d channel select logic
section 10: a/d converter motorola page 65 mc68hc05v7 specification rev. 1.0 section 10 a /d converter the mc68hc705v7 includes a 16 channel, 8-bit, multiplexed input, successive approximation a/d converter. when the device is packaged (in a 56-pin sdip), pin number restrictions require that 8 channels, an8 through an15, are not bonded out. 10.1 analog section 10.1.1 ratiometric conversion the a/d is ratiometric, with two dedicated pins supplying the reference voltages (v refh and v refl ) . an input voltage equal to v refh converts to $ff (full scale) and an input voltage equal to v refl converts to $00. an input voltage greater than v refh will convert to $ff with no overflow indication. for ratiometric conversions, the source of each analog input should use v refh as the supply voltage and be referenced to v refl . 10.1.2 v refh and v refl the reference supply for the converter uses two dedicated pins rather than being driven by the system power supply lines because the voltage drops in the bonding wires of those heavily loaded pins would degrade the accuracy of the a/d conversion. v refh and v refl can be any voltage between v ssa1 and v cca , as long as v refh > v refl ; however, the accuracy of conversions is tested and guaranteed only for v refl = v ssa1 and v refh = v cca . 10.1.3 accuracy and precision the 8-bit conversions shall be accurate to within 1 1 / 2 lsb including quantization. 10.2 conversion process the a/d reference inputs are applied to a precision internal digital-to-analog converter. control logic drives this d/a and the analog output is successively compared to the selected analog input which was sampled at the beginning of the conversion time. the conversion process is monotonic and has no missing codes. 10.3 digital section 10.3.1 conversion times each channel of conversion takes 32 clock cycles, which must be at a frequency equal to or greater than 1 mhz.
motorola section 10: a/d converter page 66 mc68hc05v7 specification rev. 1.0 10.3.2 internal vs. master oscillator if the mcu bus (e clock) frequency is less than 1.0 mhz, an internal rc oscillator (nominally 1.5 mhz) must be used for the a/d conversion clock. this selection is made by setting the adrc bit in the a/d status and control registers to 1. in stop mode, the internal rc oscillator is turned off automatically, though the a/d subsystem remains enabled (adon remains set). in wait mode the a/d subsystem remains functional. see 10.6 a/d during wait mode. when the internal rc oscillator is being used as the conversion clock, three limitations apply: 1. the conversion complete flag (coco) must be used to determine when a conversion sequence has been completed, due to the frequency tolerance of the rc oscillator and its asynchronism with regard to the mcu e clock. 2. the conversion process runs at the nominal 1.5 mhz rate but the conversion results must be transferred to the mcu result registers synchronously with the mcu e clock so conversion time is limited to a maximum of one channel per e cycle. 3. if the system clock is running faster than the rc oscillator, the rc oscillator should be turned off, and the system clock used as the conversion clock. 10.3.3 multi-channel operation a multiplexer allows the a/d converter to select one of sixteen external analog signals and four internal reference sources. 10.4 a/d status and control register (adscr) the following paragraphs describe the function of the a/d status and control register. figure 10-1: a/d status and control register 10.4.1 coco - conversions complete this read-only status bit is set when a conversion is completed, indicating that the a/d data register contains valid results. this bit is cleared whenever the a/d status and control register is written and a new conversion is automatically started, or whenever the a/d data register is read. once a conversion has been started by writing to the a/d status and control register, conversions of the selected channel will continue every 32 cycles until the a/d status and control register is written again. in this continuous conversion mode the a/d data register will be filled with new data, and the coco bit set, every 32 cycles. data from the previous conversion will be overwritten regardless of the state of the coco bit prior to writing. 0 000000 0 reset: coco adon ch4 ch3 ch2 ch1 ch0 adrc $1e
section 10: a/d converter motorola page 67 mc68hc05v7 specification rev. 1.0 10.4.2 adrc - rc oscillator control when adrc is set, the a/d section runs on the internal rc oscillator instead of the cpu clock. the rc oscillator requires a time t rcon to stabilize, and results can be inaccurate during this time. 10.4.3 adon - a/d on when the a/d is turned on (adon = 1), it requires a time t adon for the current sources to stabilize, and results can be inaccurate during this time. this bit turns on the charge pump. 10.4.4 ch4:ch0 - channel select bits ch4, ch3, ch2, ch1, and ch0 form a 5-bit field which is used to select one of twenty a/ d channels, including four internal references. channels $0-7 correspond to port d input pins on the mcu. channels $8-f correspond to port e input pins on the mcu and are not bonded out in 56 pin packaged parts. channels $10-13 are used for internal reference points. in single-chip mode, channel $13 is reserved and converts to $00. the following table shows the signals selected by the channel select field. table 10-1: a/d channel assignments 10.5 a/d data registers an 8-bit result register is provided. this register is updated each time the coco bit is set. figure 10-2: a/d data register ch4:ch0 signal 00-07 an0-7 08-0f an8-15 10 v refh 11 (v refh - v refl )/2 12 v refl 13 factory test 14 unused d7 d5 d4 d3 d2 d1 d0 d6 $1d * * * * accuracy not guaranteed for internal channels
motorola section 10: a/d converter page 68 mc68hc05v7 specification rev. 1.0 10.6 a/d during wait mode the a/d converter continues normal operation during wait mode. to decrease power consumption during wait, it is recommended that both the adon and adrc bits in the a/ d status and control registers be cleared if the a/d converter is not being used. if the a/ d converter is in use and the system clock rate is above 1.0 mhz, it is recommended that the adrc bit be cleared. note: as the a/d converter continues to function normally in wait mode, the coco bit is not cleared. 10.7 a/d during stop mode in stop mode the comparator and charge pump are turned off and the a/d ceases to function. any pending conversion is aborted. when the clocks begin oscillation upon leaving the stop mode, a finite amount of time passes before the a/d circuits stabilize enough to provide conversions to the specified accuracy. normally, the delays built into the device when coming out of stop mode are sufficient for this purpose, therefore no explicit delays need to be built into the software. note: although the comparator and charge pump are disabled in stop mode, the a/d data and status/control registers are not modified. disabling the a/d prior to entering stop mode will not effect the stop mode current consumption.
section 11: 16-bit timer motorola page 69 mc68hc05v7 specification rev. 1.0 section 11 1 6-bit timer the timer consists of a 16-bit, free-running counter driven by a fixed divide-by-four prescaler. this timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. pulse widths can vary from several microseconds to many seconds. figure 11-1: 16-bit timer block diagram . because the timer has a 16-bit architecture, each specific functional segment (capability) is represented by two registers. these registers contain the high and low byte of that functional segment. access of the high byte inhibits that specific timer function until the low byte is also accessed. note: the i bit in the ccr should be set while manipulating both the high and low byte register of a specific timer function to ensure that an interrupt does not occur. figure 11-1: 16-bit timer block diagram input capture register clock internal bus output compare register high byte low byte $16 $17 ??? /4 internal processor 16-bit free running counter counter alternate register 8-bit buffer high byte low byte $1a $1b $18 $19 high byte low byte $14 $15 output compare circuit overflow detect circuit edge detect circuit timer status reg. icf ocf tof $13 icie iedg olvl output level reg. reset timer control reg. $12 output level (tcmp) interrupt circuit toie ocie edge input (tcap) d clk c q pb6 pb7
motorola section 11: 16-bit timer page 70 mc68hc05v7 specification rev. 1.0 11.1 counter register - $18:$19, $1a:$1b the key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. the prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0 mhz. the counter is incremented during the low portion of the internal bus clock. software can read the counter at any time without affecting its value. the double-byte, free-running counter can be read from either of two locations, $18-$19 (counter register) or $1a-$1b (counter alternate register). a read from only the least significant byte (lsb) of the free-running counter ($19, $1b) receives the count value at the time of the read. if a read of the free-running counter or counter alternate register first addresses the most significant byte (msb) ($18, $1a), the lsb ($19, $1b) is transferred to a buffer. this buffer value remains fixed after the first msb read, even if the user reads the msb several times. this buffer is accessed when reading the free-running counter or counter alternate register lsb ($19 or $1b) and, thus, completes a read sequence of the total counter value. in reading either the free-running counter or counter alternate register, if the msb is read, the lsb must also be read to complete the sequence. the counter alternate register differs from the counter register in one respect: a read of the counter register msb can clear the timer overflow flag (tof). therefore, the counter alternate register can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the tof. the free-running counter is configured to $fffc during reset and is a read-only register but only when the timer is enabled. during a power-on reset, the counter is also preset to $fffc and begins running only after the ton bit in the timer control register is set. because the free-running counter is 16 bits preceded by a fixed divided-by-four prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. when the counter rolls over from $ffff to $0000, the tof bit is set. an interrupt can also be enabled when counter roll-over occurs by setting its interrupt enable bit (toie). note: the i bit in the ccr should be set while manipulating both the high and low byte register of a specific timer function to ensure that an interrupt does not occur. 11.2 output compare register - $16:$17 the 16-bit output compare register is made up of two 8-bit registers at locations $16 (msb) and $17 (lsb). the output compare register is used for several purposes, such as indicating when a period of time has elapsed. all bits are readable and writable and are not altered by the timer hardware or reset. if the compare function is not needed, the two bytes of the output compare register can be used as storage locations. the output compare register contents are continually compared with the contents of the free-running counter. if a match is found, the corresponding output compare flag (ocf) bit is set and the corresponding output level (olvl) bit is clocked to an output level register. the output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed time-out. an interrupt can also
section 11: 16-bit timer motorola page 71 mc68hc05v7 specification rev. 1.0 accompany a successful output compare provided the corresponding interrupt enable bit (ocie) is set. after a processor write cycle to the output compare register containing the msb ($16), the output compare function is inhibited until the lsb ($17) is also written. the user must write both bytes (locations) if the msb is written first. a write made only to the lsb ($17) will not inhibit the compare function. the free-running counter is updated every four internal bus clock cycles. the minimum time required to update the output compare register is a function of the program rather than the internal hardware. the processor can write to either byte of the output compare register without affecting the other byte. the output level (olvl) bit is clocked to the output level register regardless of whether the output compare flag (ocf) is set or clear. 11.3 input capture register - $14:$15 two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. the level transition that triggers the counter transfer is defined by the corresponding input edge bit (iedg). reset does not affect the contents of the input capture register. the result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. this delay is required for internal synchronization. resolution is one count of the free-running counter, which is four internal bus clock cycles. the free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (icf) is set or clear. the input capture register always contains the free-running counter value that corresponds to the most recent input capture. after a read of the input capture register msb ($14), the counter transfer is inhibited until the lsb ($15) is also read. this characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. a read of the input capture register lsb ($15) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock. note: the input capture pin (tcap) and the output compare pin (tcmp) are shared with pb7 and pb6 respectively. the timer? tcap input is always connected to pb7. pb6 is the timer? tcmp pin if the oce bit in the miscellaneous control register is set. see 7.2.2oce - output compare enable .
motorola section 11: 16-bit timer page 72 mc68hc05v7 specification rev. 1.0 11.4 timer control register (tcr) - $12 the tcr is a read/write register containing six control bits. three bits control interrupts associated with the timer status register flags icf, ocf and tof. figure 11-2: timer control register - $12 11.4.1 icie - input capture interrupt enable 1 - interrupt enabled 0 - interrupt disabled 11.4.2 ocie - output compare interrupt enable 1 - interrupt enabled 0 - interrupt disabled 11.4.3 toie - timer overflow interrupt enable 1 - interrupt enabled 0 - interrupt disabled 11.4.4 ton - timer on when disabled, the timer is initialized to the reset condition. 1 - timer enabled 0 - timer disabled 11.4.5 iedg - input edge value of input edge determines which level transition on tcap pin will trigger free- running counter transfer to the input capture register. reset clears this bit. 1 - positive edge 0 - negative edge 11.4.6 olvl - output level value of output level is clocked into output level register by the next successful output compare and will appear on the tcmp pin. 1 - high output 0 - low output 11.5 timer status register (tsr) - $13 the tsr is a read-only register containing three status flag bits. figure 11-3: timer status register - $13 icie ocie toie 0 0 ton iedg olvl reset $12 00 0 0 0 0 00 icfocftof00000 reset $13 00 0 0 0 0 00
section 11: 16-bit timer motorola page 73 mc68hc05v7 specification rev. 1.0 11.5.1 icf - input capture flag 1 - flag set when selected polarity edge is sensed by input capture edge detector 0 - flag cleared when tsr and input capture low register ($15) are accessed reset clears this bit. 11.5.2 ocf - output compare flag 1 - flag set when output compare register contents match the free-running counter contents 0 - flag cleared when tsr and output compare low register ($17) are accessed reset clears this bit. 11.5.3 tof - timer overflow flag 1 - flag set when free-running counter transition from $ffff to $0000 occurs 0 - flag cleared when tsr and counter low register ($19) are accessed reset clears this bit. 11.5.4 bits 0-4 - not used always read zero. accessing the timer status register satisfies the first condition required to clear status bits. the remaining step is to access the register corresponding to the status bit. a problem can occur when using the timer overflow function and reading the free-running counter at random times to measure an elapsed time. without incorporating the proper precautions into software, the timer overflow flag could unintentionally be cleared if: 1. the timer status register is read or written when tof is set, and 2. the msb of the free-running counter is read but not for the purpose of servicing the flag. the counter alternate register at address $1a and $1b contains the same value as the free- running counter (at address $18 and $19); therefore, this alternate register can be read at any time without affecting the timer overflow flag in the timer status register. 11.6 timer during wait mode the cpu clock halts during the wait mode, but the timer remains active if turned on prior to entering wait mode. if interrupts are enabled, a timer interrupt will cause the processor to exit the wait mode. 11.7 timer during stop mode in the stop mode, the timer stops counting and holds the last count value if stop is exited by an interrupt. if reset is used, the counter is forced to $fffc. during stop, if the timer is on and at least one valid input capture edge occurs at the tcap pin, the input
motorola section 11: 16-bit timer page 74 mc68hc05v7 specification rev. 1.0 capture detect circuit is armed. this does not set any timer flags nor wake up the mcu, but when the mcu does wake up, there is an active input capture flag and data from the first valid edge that occurred during the stop mode. if reset is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred. figure 11-4: tcap timing tcap t tltl t tl t th
section 12: core timer motorola page 75 mc68hc05v7 specification rev. 1.0 section 12 c ore t imer the core timer for this device is a 12-stage multifunctional ripple counter. the features include timer over flow, power-on reset (por), real time interrupt (rti), and cop watchdog timer. figure 12-1: core timer block diagram cop clear internal bus $09 core timer counter register (ctcr) 5-bit counter ctof rtif tofe rtie rt1 interrupt circuit $08 rti select circuit status register rt0 timer control & overflow circuit detect cop watchdog timer ( ? 8) to reset logic 8 8 rtfc tofc e/2 10 tcbp ctcsr ctcr internal peripheral clock (e) to interrupt logic rti out e / 2 12 por e/2 2 div /4 e / 2 9 e / 2 14 e / 2 13 e / 2 12 e / 2 11 2 3
motorola section 12: core timer page 76 mc68hc05v7 specification rev. 1.0 as seen in figure 6-1, the internal peripheral clock is divided by four then drives an 8-bit ripple counter. the value of this 8-bit ripple counter can be read by the cpu at any time by accessing the core timer counter register (ctcr) at address $09. a timer overflow function is implemented on the last stage of this counter, giving a possible interrupt rate of the internal peripheral clock(e)/1024. this point is then followed by two more stages, with the resulting clock (e/2048) driving the real time interrupt circuit (rti). the rti circuit consists of three divider stages with a 1 of 4 selector. the output of the rti circuit is further divided by eight to drive the mask optional cop watchdog timer circuit. the rti rate selector bits, and the rti and ctof enable bits and flags are located in the timer control and status register at location $08. 12.1 core timer ctrl & status register (ctcsr) $08 the ctcsr contains the timer interrupt flag, the timer interrupt enable bits, and the real time interrupt rate select bits. figure 12-2 shows the value of each bit in the ctcsr when coming out of reset. figure 12-2: core timer control and status register 12.1.1 ctof - core timer over flow ctof is a read-only status bit set when the 8-bit ripple counter rolls over from $ff to $00. clearing the ctof is done by writing a ??to tofc. writing to this bit has no effect. reset clears ctof. 12.1.2 rtif - real time interrupt flag the real time interrupt circuit consists of a three stage divider and a 1 of 4 selector. the clock frequency that drives the rti circuit is e/2**11 (or e/2048) with three additional divider stages giving a maximum interrupt period of 7.8 milliseconds at a bus rate of 2.1 mhz. rtif is a clearable, read-only status bit and is set when the output of the chosen (1 of 4 selection) stage goes active. clearing the rtif is done by writing a ??to rtfc. writing has no effect on this bit. reset clears rtif. 12.1.3 tofe - timer over flow enable when this bit is set, a cpu interrupt request is generated when the ctof bit is set. reset clears this bit. 12.1.4 rtie - real time interrupt enable when this bit is set, a cpu interrupt request is generated when the rtif bit is set. reset clears this bit. 12.1.5 tofc - timer over flow flag clear when a ??is written to this bit, ctof is cleared. writing a ??has no effect on the ctof bit. this bit always reads as zero. ctof tofe rtie tofc rtfc rt1 rt0 rtif $08 0 000011 0 reset:
section 12: core timer motorola page 77 mc68hc05v7 specification rev. 1.0 12.1.6 rtfc - real time interrupt flag clear when a ??is written to this bit, rtif is cleared. writing a ??has no effect on the rtif bit. this bit always reads as zero. 12.1.7 rt1:rt0 - real time interrupt rate select these two bits select one of four taps from the real time interrupt circuit. table 12-1 shows the available interrupt rates with a 2.1 and 1.05mhz bus clock. reset sets these two bits which selects the lowest periodic rate and gives the maximum time in which to alter these bits if necessary. care should be taken when altering rt0 and rt1 if the time-out period is imminent or uncertain. if the selected tap is modified during a cycle in which the counter is switching, an rtif could be missed or an additional one could be generated. to avoid problems, the cop should be cleared before changing rti taps. table 12-1: rti and cop rates at 2.1 mhz 12.2 computer operating properly (cop) reset the cop watchdog timer function is implemented on this device by using the output of the rti circuit and further dividing it by eight. the minimum cop reset rates are listed in table 12-1. if the cop circuit times out, an internal reset is generated and the normal reset vector is fetched. preventing a cop time-out, or clearing the cop, is accomplished by writing a ??to bit 0 of address $3ff0. when the cop is cleared, only the final divide by eight stage (output of the rti) is cleared. if the cop watchdog timer is allowed to time-out, an internal reset is generated to reset the mcu. in addition the reset pin will be pulled low for a minimum of 3 e clock cycle for emulation purposes. during a chip reset (regardless of the source), the entire core timer counter chain is cleared. the cop will remain enabled after execution of the wait instruction and all associated operations apply. if the stop instruction is disabled, execution of stop instruction will cause an internal reset. this cop? objective is to make it impossible for this part to become ?tuck?or ?ocked-up and to be sure the cop is able to ?escue?the part from any situation where it might entrap itself in an abnormal or unintended behavior. this function is a mask option. 11 rt1:rt0 min. cop rates 00 01 10 2 14 /e rti rate 2 11 /e 2 12 /e 2 13 /e 15.60 ms 1.95 ms 3.90 ms 7.80 ms 7.80 ms 0.97 ms 1.95 ms 3.90 ms 109.23ms 13.65ms 27.31ms 54.61ms 54.61 ms 6.83 ms 13.65 ms 27.31 ms (2 17 -2 14 )/e (2 14 -2 11 )/e (2 15 -2 12 )/e (2 16 -2 13 )/e 1.05 mhz 2.1 mhz 1.05 mhz 2.1 mhz
motorola section 12: core timer page 78 mc68hc05v7 specification rev. 1.0 12.3 core timer counter register (ctcr) $09 the timer counter register is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. this counter is clocked by the cpu clock (e/4) and can be used for various functions including a software input capture. extended time periods can be attained using the tof function to increment a temporary ram storage location thereby simulating a 16-bit (or more) counter. figure 12-3: timer counter register the power-on cycle clears the entire counter chain and begins clocking the counter. after 4064 cycles, the power-on reset circuit is released which again clears the counter chain and allows the device to come out of reset. at this point, if reset is not asserted, the timer will start counting up from zero and normal device operation will begin. when reset is asserted anytime during operation (other than por), the counter chain will be cleared. 12.4 timer during wait mode the cpu clock halts during the wait mode, but the timer remains active. if interrupts are enabled, a timer interrupt will cause the processor to exit the wait mode. the cop is always enabled while in user mode. d7 d5 d4 d3 d2 d1 d0 d6 $09
section 13: pulse width modulator motorola page 79 mc68hc05v7 specification rev. 1.0 section 13 p ulse width modulator the pulse width modulator (pwm) system has one 6-bit channel (pwma). preceding the 6-bit ( ? 64) pwm are two programmable prescalers.the pwm frequency is selected by choosing the desired divide option from the programmable prescalers. note that the pwm clock input is f osc , which is twice the bus frequency. the pwm frequency will be f osc / (psa+psb+64) where psa and psb are the values selected by the a and b prescaler and 64 comes from the 6-bit modulus counter. see table 13-1 for precise values. e is the internal bus frequency fixed to half of the external oscillator frequency. figure 13-1: pwm block diagram 13.1 functional description the pwm is capable of generating signals from 0% to 100% duty cycle. a $00 in the pwm data register yields an ?ow?output (0%), but a $3f yields a duty of 63/64. to achieve the 100% duty (?igh?output), the polarity control bit is set to zero while the data register has $00 in it. when not in use, the pwm system can be shut off to save power by clearing the clock rate select bits psa0 and psa1 in pwmcr. writes to the pwm data register are buffered and can therefore be performed at any time without affecting the output signal. when the pwm subsystem is enabled, a write to the pwm control register will become effective immediately. 6-bit counter ( ? 64) pwm data register modulus & comparator pwm pin logic pwma ? 1, ? 8, ? 16 f osc psa0 psa1 pwm control register and buffer hc05 data bus pol pwm data buffer sclk ? 1-16 psb2 psb3 psb0 psb1 rclk integer divide
motorola section 13: pulse width modulator page 80 mc68hc05v7 specification rev. 1.0 when the pwm subsystem is enabled, a write to the pwm data register will not become effective until the following condition has been met. the end of the current pwm period has occurred, at which time the new data value is loaded into the pwm data register. however, should a write to the registers be performed when the pwm subsystem is disabled, the data is transferred immediately. all registers are updated after the pwm data register is written to and the end of a pwm cycle occurs. the pwm output can have an active high or an active low pulse under software control using the pol (polarity) bit as shown in figure 13-2 and figure 13-3. figure 13-2: pwm waveform examples (pol = 1) figure 13-3: pwm waveform examples (pol = 0) $05 $3f $1f pwm register = $x0 t $05 $1f pwm register = $x0 t $3f
section 13: pulse width modulator motorola page 81 mc68hc05v7 specification rev. 1.0 13.2 registers associated with the pwm system, there is a pwm data register and a control register. the following registers can be written to and read at any time. data written to the data register is held in a buffer and transferred to the pwm data register at the end of a pwm cycle. reads of this register will always result in the read of the pwm data register and not the buffer. upon reset the user should write to the data register prior to enabling the pwm system (for example, prior to setting the psa and psb bits for pwm input clock rate). this will avoid an erroneous duty cycle from being driven. during regular user mode the user should write to the pwm data data register after writing the pwm control register. figure 13-4: pwm write sequences 13.2.1 pwm control figure 13-5: pwm control register psa1, psa0, psb3-psb0- pwm clock rate these bits select the input clock rate and determines the period, as shown in table 13-1. note that some output frequencies can be obtained with more than one combination of psa table 13-1: pwm clock rate psa1:psa0 psb3-psb0 rclk sclk pwm out 00 xxxx off off off 01 0000-1111 f osc /1 f osc /1-f osc /16 f osc /64- f osc /1024 10 0000-1111 f osc /8 f osc /8-f osc /128 f osc /512- f osc /8192 initialize pwm data 0 write pwm control or reset por write pwm control write pwm data 1 n y psa1 -- -- psb2 psb1 psb0 psa0 $31 0--00 0 0 0 reset: -- psb3
motorola section 13: pulse width modulator page 82 mc68hc05v7 specification rev. 1.0 and psb values. for instance a pwm output of e/512 can be obtained with either psa1:psa0 = 10 and psb3-psb0 = 0001 or psa1:psa0 = 01 and psb3-psb0 = 1000. this scheme allows for 38 unique frequency selections. 13.2.2 pwm data registers the pwm system has one 8-bit data register which hold the duty cycle for each pwm output in the least significant 6 bits. the data bits in this register are unaffected by reset. figure 13-6: pwm data register pol - pwm polarity 1 = pwm pulse is active high. 0 = pwm pulse is active low. 13.3 pwm during wait mode the pwm continues normal operation during wait mode. to decrease power consumption during wait, it is recommended that the rate select bits in the pwm control register be cleared if the pwm is not being used. 13.4 pwm during stop mode in stop mode the oscillator is stopped causing the pwm to cease functioning. any signal in process is aborted in whatever phase the signal happens to be in. 13.5 pwm during reset upon reset the psa0 and psa1 bits in pwm control are cleared. this disables the pwm system and sets the pwma output low. the user should write to the data registers prior to enabling the pwm system (for example, prior to setting psa1 or psa0). this will avoid an erroneous duty cycle from being driven. 11 0000-1111 f osc /16 f osc /16-f osc / 256 f osc /1024- f osc /16384 table 13-1: pwm clock rate psa1:psa0 psb3-psb0 rclk sclk pwm out 1 reset: pol d5 d4 d3 d2 d1 d0 - $30
section 14: serial peripheral interface motorola page 83 mc68hc05v7 specification rev. 1.0 section 14 s erial peripheral interface the serial peripheral interface (spi) is an interface which allows several mc68hc05 mcus, or mc68hc05 mcu plus peripheral devices, to be interconnected within a single printed circuit board. in an spi, separate wires are required for data and clock. in the spi format, the clock is not included in the data stream and must be furnished as a separate signal. an spi system may be configured in one containing one master mcu and several slave mcus, or in a system in which an mcu is capable of being a master or a slave. features include: full duplex, three-wire synchronous transfers master or slave operation internal mcu clock divided by 2 (maximum) master bit frequency internal mcu clock (maximum) slave bit frequency four programmable master bit rates programmable clock polarity and phase end of transmission interrupt flag write collision flag protection master-master mode fault protection capability 14.1 spi signal description the four basic signals (mosi, miso, sck, ss ) are described in the following paragraphs. each signal function is described for both the master and slave mode.
motorola section 14: serial peripheral interface page 84 mc68hc05v7 specification rev. 1.0 the spi forces the direction on some of the pin to output in order to function properly. figure 14-1: data clock timing diagram 14.1.1 master in slave out (miso/pf3) the miso line is configured as an input in a master device and as an output in a slave device. it is one of the two lines that transfer serial data in one direction, with the most significant bit sent first. the miso line of a slave device is placed in the high-impedance state if the slave is not selected. 14.1.2 master out slave in (mosi/pf2) the mosi line is configured as an output in a master device and as an input in a slave device. it is one of the two lines that transfer serial data in one direction with the most significant bit sent first. 14.1.3 serial clock (sck/pf1) the master clock is used to synchronize data movement both in and out of the device through its mosi and miso lines. the master and slave devices are capable of exchanging a byte of information during a sequence of eight clock cycles. since sck is generated by the master device, this line becomes an input on a slave device. as shown in figure 14-1, four possible timing relationships may be chosen by using control bits cpol and cpha in the serial peripheral control register (spcr). both master and slave devices must operate with the same timing. the master device always places data on the mosi line a half-cycle before the clock edge (sck), in order for the slave device to latch the data. two bits (spr0 and spr1) in the spcr of the master device select the clock rate. in a slave device, spr0 and spr1 have no effect on the operation of the spi. internal strobe for data capture (all modes) msb6543210 ss sck sck sck sck miso/mosi (cpol=0, cpha=0) (cpol=0, cpha=1) (cpol=1, cpha=0) (cpol=1, cpha=1)
section 14: serial peripheral interface motorola page 85 mc68hc05v7 specification rev. 1.0 14.1.4 slave select (ss /pf0) the slave select (ss ) input line is used to select a slave device. it has to be low prior to data transactions and must stay low for the duration of the transaction.the ss line on the master must be tied high. if it goes low, a mode fault error flag (modf) is set in the spsr. when cpha=0, the shift clock is the or of ss with sck. in this clock phase mode, ss must go high between successive characters in an spi message. when cpha=1, ss may be left low for several spi characters. in cases where there is only one spi slave mcu, its ss line could be tied to v ss as long as cpha=1 clock modes are used. the ss pin is shared with the pf0 pin. see 9.4port f for additional information on the ss pin. 14.2 functional description figure 14-2 shows a block diagram of the serial peripheral interface circuitry. when a master device transmits data to a slave via the mosi line, the slave device responds by sending data to the master device via the master? miso line. this implies full duplex transmission with both data out and data in synchronized with the same clock signal. thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receive-full status bits. a single status bit (spif) is used to signify that the i/o operation has been completed. the spi is double buffered on read, but not on write. if a write is performed during data transfer, the transfer occurs uninterrupted, and the write will be unsuccessful. this condition will cause the write collision (wcol) status bit in the spsr to be set. after a data byte is shifted, the spif flag of the spsr is set.
motorola section 14: serial peripheral interface page 86 mc68hc05v7 specification rev. 1.0 figure 14-2: serial peripheral interface block diagram in the master mode, the sck pin is an output. it idles high or low, depending on the cpol bit in the spcr, until data is written to the shift register, at which point eight clocks are generated to shift the eight bits of data and then sck goes idle again. in a slave mode, the slave select start logic receives a logic low at the ss pin and a clock at the sck pin. thus, the slave is synchronized with the master. data from the master is received serially at the mosi line and loads the 8-bit shift register. after the 8-bit shift register is loaded, its data is parallel transferred to the read buffer. during a write cycle, data is written into the shift register, then the slave waits for a clock train from the master to shift the data out on the slave? miso line. figure 14-3 illustrates the mosi, miso, sck, and ss master-slave interconnections. divider ? 2 ? 4 ? 16 ? 32 select 8-bit shift reg read data buff msb lsb s m m s s m pin control logic clock clock logic spi clock (master) mstr spe spie spe mstr cpha cpol spr1 spr0 spi control register internal data bus spi interrupt request spi status register spr1 spr0 spi control spif wcol modf internal mcu clock pf1/ pf0/ pf2/ pf3/ miso mosi sck ss
section 14: serial peripheral interface motorola page 87 mc68hc05v7 specification rev. 1.0 figure 14-3: serial peripheral interface master-slave interconnection 14.3 spi registers there are three registers in the spi which provide control, status, and data storage functions. these registers are called the serial control register (spcr), serial peripheral status register (spsr), and serial peripheral data i/o register (spdr) and are described in the following paragraphs. 14.3.1 serial peripheral control register (spcr) figure 14-4: spi control register (spcr) spie - serial peripheral interrupt enable 0 = spif interrupts disabled 1 = spi interrupt is spif=1 spe - serial peripheral system enable 0 = spi system off 1 = spi system on. port f becomes spi pins. ss is a special case. see 9.4 port f for additional information. mstr - master mode select 0 = slave mode 1 = master mode 8-bit shift register 8-bit shift register miso mosi miso mosi spi clock generator sck sck slave master ss ss v dd spie mstr cpol cpha spr1 spr0 spe $0a 0 0001uu 0 reset:
motorola section 14: serial peripheral interface page 88 mc68hc05v7 specification rev. 1.0 cpol - clock polarity when the clock polarity bit is cleared and data is not being transferred, a steady state low value is produced at the sck pin of the master device. conversely, if this bit is set, the sck pin will idle high. this bit is also used in conjunction with the clock phase control bit to produce the desired clock-data relationship between master and slave. figure 14-1: data clock timing diagram. cpha - clock phase the clock phase bit, in conjunction with the cpol bit, controls the clock-data relationship between master and slave. the cpol bit can be thought of as simply inserting an inverter in series with the sck line. the cpha bit selects one of two fundamentally different clocking protocols. when cpha=0, the shift clock is the or of sck with ss . as soon as ss goes low, the transaction begins and the first edge on sck invokes the first data sample. when cpha=1, the ss pin may be thought of as a simple output enable control. figure 14-1: data clock timing diagram. spr1 and spr0 - spi clock rate selects these two bits select one of four baud rates (figure 14-5) to be used as sck if the device is a master; however, they have no effect in the slave mode. figure 14-5: serial peripheral rate selection 14.3.2 serial peripheral status register (spsr) figure 14-6: spi status register (spsr) spif - spi transfer complete flag the serial peripheral data transfer flag bit is set upon completion of data transfer between the processor and external device. if spif goes high, and if spie is set, a serial peripheral interrupt is generated. clearing the spif bit is accomplished by reading the spsr (with spif set) followed by an access of the spdr. unless spsr is read (with spif set) first, attempts to write to spdr are inhibited. spr1 spr0 0 0 0 1 1 0 1 1 int mcu clock divided by 2 4 16 32 spif modf wcol $0b 0 000000 0 reset:
section 14: serial peripheral interface motorola page 89 mc68hc05v7 specification rev. 1.0 wcol - write collision the write collision bit is set when an attempt is made to write to the serial peripheral data register while data transfer is taking place. if cpha is zero, a transfer is said to begin when ss goes low and the transfer ends when ss goes high after eight clock cycles on sck. when cpha is one, a transfer is said to begin the first time sck becomes active while ss is low and the transfer ends when the spif flag gets set. clearing the wcol bit is accomplished by reading the spsr (with wcol set) followed by an access to spdr. bit 5 - not implemented this bit always reads zero. modf - mode fault the mode fault flag indicates that there may have been a multi-master conflict for system control and allows a proper exit from system operation to a reset or default system state. the modf bit is normally clear, and is set only when the master device has its ss pin pulled low. setting the modf bit affects the internal serial peripheral interface system in the following ways: spi interrupt is generated if spie=1. spe bit is cleared. this disables the spi. mstr bit is cleared, thus forcing the device into the slave mode. clearing the modf bit is accomplished by reading the spsr (with modf set), followed by a write to the spcr. control bits spe and mstr may be restored to their original state by user software after the modf bit has been cleared. it is also necessary to restore ddrd after a mode fault. bits 3-0 - not implemented these bits always read zero. 14.3.3 serial peripheral data i/o register (spdr) the serial peripheral data i/o register is used to transmit and receive data on the serial bus. only a write to this register will initiate transmission/reception of another byte, and this will only occur in the master device. at the completion of transmitting a byte of data, the spif status bit is set in both the master and slave devices. when the user reads the serial peripheral data i/o register, a buffer is actually being read. the first spif must be cleared by the time a second transfer of the data from the shift register to the read buffer is initiated, or an overrun condition will exist. in cases of overrun, the byte that causes the overrun is lost. a write to the serial peripheral data i/o register is not buffered and places data directly into the shift register for transmission. spd7 spd5 spd4 spd3 spd2 psd1 spd0 spd6 $0c - ------ - reset:
motorola section 14: serial peripheral interface page 90 mc68hc05v7 specification rev. 1.0 14.4 spi in stop mode when the mcu enters the stop mode, the baud rate generator which drives the spi shuts down. this essentially stops all master mode spi operation; thus, the master spi is unable to transmit or receive any data. if the stop instruction is executed during an spi transfer, that transfer is halted until the mcu exits the stop mode (provided it is an exit resulting from a viable interrupt source). if the stop mode is exited by a reset, then the appropriate control/ status bits are cleared and the spi is disabled. if the device is in the slave mode when the stop instruction is executed, the slave spi will still operate. it can still accept data and clock information in addition to transmitting its own data back to a master device. at the end of a possible transmission with a slave spi in the stop mode, no flags are set until a viable interrupt results in an mcu "wake up". caution should be observed when operating the spi (as a slave) during the stop mode because none of the protection circuitry (write collision, mode fault, etc.) is active. it should also be noted that when the mcu enters the stop mode all enabled output drivers (miso, mosi, and sclk ports) remain active and any sourcing currents from these outputs will be part of the total supply current required by the device. 14.5 spi in wait mode the spi subsystem remains active in wait mode. therefore, it is consuming power. if it is desired to reduce power, the spi should be shut off prior to entering wait mode. a non- resetexit from wait mode will result in the state of the spi being unchanged. a reset exit will return the spi to its reset state, which is disabled.
section 15: message data link controller motorola page 91 mc68hc05v7 specification rev. 1.0 section 15 message data link controller the message data link controller (mdlc) provides access to an external serial communication multiplex bus, operating according to the sae j1850 protocol. key features of the mdlc include: sae j1850 compatible gm class 2 compatible 10.4 kbps variable pulse width (vpw) bit format digital noise filter collision detection two 11-byte receive buffers, one 11-byte transmit buffer hardware crc generation and checking two power saving modes with automatic wake up on network activity polling and cpu interrupts available receive block mode supported coexists with devices supporting 4x mode auto retry following loss of arbitration in-frame response not supported low voltage protection
motorola section 15: message data link controller page 92 mc68hc05v7 specification rev. 1.0 15.1 outline the cpu interface contains the software addressable registers and provides the link between the cpu and the tx and rx buffers. the tx and rx buffers provide storage for data received and data to be transmitted onto the j1850 bus. the protocol handler is responsible for the encoding and decoding of data bits and special message symbols during transmission and reception. the mux interface provides the link between the mdlc digital section and the analog physical interface. the wave shaping, driving, and digitizing of data is performed by the physical interface. note: the bus data rate depends upon the microcontroller oscillator frequency (f osc ) and the mdlc rate selection control bits (r0, r1). the correct combination for the application must be chosen in order for j1850 bus communications to take place. see 15.2.2.3 r1, r0 - rate select . physical interface to cpu protocol handler mux interface cpu interface rx/tx buffers to j1850 bus mdlc
section 15: message data link controller motorola page 93 mc68hc05v7 specification rev. 1.0 15.1.1 mdlc operating modes the mdlc has five main modes of operation that interact with the power supplies, pins, the and rest of the mcu as shown below. 15.1.2 mode descriptions 15.1.2.1 power off this mode is entered from the reset mode whenever the mcu supply voltage v dd drops below the minimum specified value to guarantee correct mdlc operation. in order to ensure that the mdlc does not enter an unknown state, it will first be placed in the reset mode before being powered down. in this mode, the pin input and output specifications are not guaranteed. v dd > v mdlc (min.) and power off figure 15-1: mdlc operating modes state diagram reset mdlc stop run v dd v mdlc (min.) stop instruction or (from any mode) mdlc wait rxms=1 or (wait instruction and wcm=1) (wait instruction and wcm=0) any mcu reset source asserted no mcu reset source asserted any mcu reset source asserted network activity or other mcu wake-up other mcu wake-up (cop, illaddr, p.u., reset, lvr, por disabled stop)
motorola section 15: message data link controller page 94 mc68hc05v7 specification rev. 1.0 15.1.2.2 reset this mode is entered from the power off mode whenever the mcu supply voltage v dd rises above the minimum specified value and some mcu reset source is asserted. in order to prevent an unknown state from being entered and to guarantee correct operation, the internal mcu reset will be asserted while the mdlc module is being powered up. this mode is entered from any other mode whenever the mcu supply voltage v dd drops below the minimum value for correct mdlc operation. when this occurs, the mdlc module will reenter the reset mode before being powered down to prevent an unknown state from being entered. the reset mode is also entered from any other mode as soon as one of the mcu? possible reset sources (for example, por, cop watchdog, reset pin etc.) is asserted. in this mode, the internal mdlc voltage references are operative, v dd is supplied to the internal circuits, which are held in their reset state and the internal mdlc system clock is running. registers will assume their reset condition. outputs are held in their programmed reset state, inputs and network activity are ignored. 15.1.2.3 run this mode is entered from the reset mode after all mcu reset sources are no longer asserted. it is entered from the mdlc wait mode whenever a message is successfully received. it is entered from the mdlc stop mode whenever network activity is sensed though messages will not be received properly until the clocks have stabilized and the cpu is also in the run mode. in this mode, normal network operation takes place. the user should ensure that all mdlc transmissions have ceased before exiting this mode. 15.1.2.4 mdlc wait this power conserving mode is automatically entered from the run mode whenever the cpu executes a wait instruction and if the wcm bit in the mcr register is previously cleared. in this mode, the mdlc internal clocks continue to run but the physical interface circuitry is placed in a low power mode and awaits a valid network message. if a valid network message is successfully received (rxms=1) a cpu interrupt request will be generated. 15.1.2.5 mdlc stop this power conserving mode is automatically entered from the run mode whenever the cpu executes a stop instruction, or if the cpu executes a wait instruction and the wcm bit in the mcr register is previously set. in this mode, the mdlc internal clocks are stopped but the physical interface circuitry is placed in a low power mode and awaits network activity. if network activity is sensed, then a cpu interrupt request will be generated, restarting the mdlc internal clocks.
section 15: message data link controller motorola page 95 mc68hc05v7 specification rev. 1.0 15.2 mdlc cpu interface 15.2.1 outline the cpu interface provides the interface between the cpu and the mdlc. it consists of 4 user registers. a full description of each register follows: physical interface to cpu protocol handler mux interface cpu interface rx/tx buffers to j1850 bus mdlc figure 15-2: mdlc user registers name addr mcr msr mtcr mrsr $000e $000f $0010 $0011
motorola section 15: message data link controller page 96 mc68hc05v7 specification rev. 1.0 15.2.2 mdlc control register (mcr) $0e this register is used to configure and control the mdlc. all bits may be read in all modes of mcu operation. bits 0, 4 and 5 may be written to only once after reset after which they become read only bits. bit 1 may always be written. bits 6 and 7 may only be set by the cpu, clears are ignored. these bits are cleared automatically by the mdlc when the appropriate action is completed. 15.2.2.1 rxbm - receive block mode this bit is set to indicate to the mdlc that the next incoming message will be a block message. (see 15.7.4 receiving a message in block mode ). if this bit is set and the rx buffer being loaded with data bytes received from the multiplex bus is filled or the last byte of the current block message has been received, a cpu interrupt request is generated (if the ie bit is set) and the rx message successful (rxms) bit will be set, just as in normal message reception. additional incoming bytes will be placed into the next available rx buffer. the rc3-0 bits of the mrsr register only reflect the byte count of the rx buffer available to the cpu and not a cumulative value of the number of bytes in the block message. once set, this bit can only be cleared automatically by the mdlc. it will be cleared following the successful reception of a message or immediately upon the receiver detecting an error (crc, invalid bit etc.), reverting the mdlc to its usual mode of operation in which normal message lengths are expected. this bit will also be cleared if both rx buffers fill, they are not serviced and further data bytes are received (block mode ?verflow?occurs). the receiver will compute a cumulative crc throughout the reception of a block message, and will not treat the crc calculation as complete until an end of data (eod) symbol is received. at this time the mdlc will automatically clear the rxbm bit indicating to the programmer that the block message has ended. 15.2.2.2 txab - transmit abort this bit is set by the programmer to abort an in-progress transmission. the subsequent actions depend upon what the transmitter is doing at the point in time when the cpu interface recognizes this command. figure 15-3: mdlc control register (mcr) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ie wcm r0 r1 reset 00100000 txab rxbm - -
section 15: message data link controller motorola page 97 mc68hc05v7 specification rev. 1.0 if this command is recognized by the mdlc while one of the first seven bits of a byte is being transmitted (non-byte boundary) then the transmission of the bit will be completed and no further bits will be sent. if this command is recognized while the last bit of a byte is being transmitted (byte boundary) then the transmission of the bit will first be completed. in order to avoid receiving nodes from interpreting the aborted transmission at a byte boundary as being the end of a normal message, the mdlc will then send two extra logic one bits. this guarantees that no aborted message will be an integral number of bytes in length and cannot be mistaken for a valid transmission. arbitration will be performed on any extra bits sent, allowing any other nodes which are also transmitting to continue. should the mdlc lose arbitration during the first extra logic one sent, the second extra logic one will not be sent and no further attempts to send the message will be made. if this command is recognized after a write to the mdlc transmit control register (mtcr), thus initiating a transmission, but before the message has begun to be sent on the j1850 bus, then no attempt to transmit that message will be made until a subsequent write to the mtcr is made. if this command is recognized between automatic transmission retry attempts, such as those following a loss of arbitration, all further attempts to resend the message will be suppressed. this bit is automatically cleared after the abort takes place or after it is determined that the mdlc was not transmitting anyway. refer to table 15-1: mdlc transmit abort function summary for a summary of the operation of the txab bit. the programmer must never write to the mtcr register while the txab bit is set, as this may have unpredictable results. table 15-1: mdlc transmit abort function summary transmit abort command mdlc action command recognized on non-byte boundary mdlc will terminate transmission immediately command recognized on byte boundary mdlc will transmit up to two extra ones command recognized before the message has started on the j1850 bus mdlc will not transmit the message command recognized during retry mdlc will not retry to transmit the message
motorola section 15: message data link controller page 98 mc68hc05v7 specification rev. 1.0 15.2.2.3 r1, r0 - rate select these bits determine the operating frequency of the mdlc. the nominal frequency (f mdlc ) of the mux interface clock must always be 1.048576 mhz in order for j1850 bus communication to take place. therefore, the value programmed into these bits is dependant upon the chosen mcu system clock frequency per the following table. in the case of r1=r0=0, the oscillator clock is used instead of e clock. the case of r1=r0=1 must not be selected for the mc68hc05v7 and mc68hc705v8. 15.2.2.4 ie - interrupt enable this bit determines whether the mdlc will generate cpu interrupt requests in the run mode. clearing the ie bit will not prevent cpu interrupt requests when exiting the mdlc stop or mdlc wait modes. when set, the mdlc will generate cpu interrupt requests. interrupt requests will be maintained until all of the interrupt request sources are cleared, by performing the specified actions upon the mdlc registers. when clear, the mdlc will not generate cpu interrupt requests. interrupts that were pending at the time that this bit is cleared may be lost. 15.2.2.5 wcm - wait clock mode this bit determines the operation of the mdlc during cpu wait mode. see 15.7.6 mdlc wait mode for more details on its use. when set, the mdlc internal operating clocks will be stopped during cpu wait mode. when clear, the mdlc internal operating clocks will stay running during cpu wait mode. table 15-2: mdlc rate selection clock frequency r1 r0 division f mdlc f osc =1.048576 mhz (f o p =524khz) 0 0 1 1.048576 mhz f o p =1.048576 mhz 0 1 1 1.048576 mhz f o p =2.097152 mhz 1 0 2 1.048576 mhz f o p =4.194304 mhz 1 1 4 1.048576 mhz
section 15: message data link controller motorola page 99 mc68hc05v7 specification rev. 1.0 15.2.3 mdlc status register (msr) $0f this register indicates the transmit and receive status of the mdlc. all bits may be read in all modes of mcu operation. bits 0,1, 4, 5, 6, and 7 will always read as zeros and can never be written to. bits 2 and 3 are reflective of cpu interrupt request signals and are asserted as long as their respective cpu interrupt request is pending. neither bit is affected by cpu interrupt requests generated when the mdlc ?akes up?from mdlc stop or mdlc wait mode. all writes to this register are ignored in all modes of mcu operation. 15.2.3.1 txms - transmitted message successfully when set this bit indicates that the tx buffer contents have been sent successfully. an access of the tx control register (mtcr) will clear this bit. 15.2.3.2 rxms - received message successfully when set, this bit indicates that one of the rx buffers contains a new message. this bit can only be cleared if both rx buffers are empty. if only one message has been received into an rx buffer by the mdlc, any access (read or write) of the mdlc rx status register (mrsr) will clear the rxms bit. if a second message is received after the rxms bit has been cleared by the cpu as it is retrieving the first message, the rxms bit will immediately be set again, and will remain set until the mrsr is accessed once the last message received is made available to the cpu. if both rx buffers contain a received message, the rxms bit will simply remain set until the mrsr register is accessed once the last message received is made available to the cpu. 15.2.3.3 txms and rxms interrupts if either the txms or the rxms bit is set, and if interrupts are enabled, an interrupt request will be made to the cpu. the interrupt service routine may poll these bits to establish the cause of the interrupt. the mechanism for clearing each of these bits will also clear the associated cpu interrupt request. alternatively, if interrupts are disabled, the cpu may poll these bits periodically to see if a change in status has occurred. figure 15-4: mdlc status register (msr) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 0 0 rxms txms 0 0 0 0 reset 00000000
motorola section 15: message data link controller page 100 mc68hc05v7 specification rev. 1.0 the mdlc will attempt to receive every message that it sends, so the rxms bit will usually be set a short time after the txms bit is set. because these bits act independently, cannot be written to, and have separate clearing mechanisms, it is not possible to inadvertently miss an interrupt. 15.2.3.4 clearing wake up interrupts although no flag bit is affected by the mdlc waking up from mdlc stop mode (entered by ?top?or ?ait?with wcm bit set previously) due to network activity, the cpu interrupt request that is generated by the wake up is cleared by an access of the mrsr register. 15.2.4 mdlc tx control register (mtcr) $10 this register controls the operation of the mdlc transmitter, including the tx buffer. all bits may be read in all modes of mcu operation. bits 4, 5, 6, and 7 will always read as zeros and can never be written to. bits 0, 1, 2, and 3 can be written to in all modes of mcu operation. 15.2.4.1 tc0,1,2,3 - transmit count these bits determine the length of the message body (not including the crc byte) to be sent. internally, they are reset to $00 following a reset. the programmer should first determine that the mdlc is ready to transmit, then load the message header and data bytes into the tx buffer, and finally write the length of the body of the message (excluding crc byte) into this register. this will cause the mdlc to initiate transmission of the contents of the tx buffer according to the j1850 protocol. once the last byte has been sent, a cyclic redundancy check (crc) byte will automatically be appended to the end of the message body. once the crc has been successfully sent, a cpu interrupt request will be generated (if the interrupt enable (ie) bit is set) and the tx message successful (txms) bit will be set in the msr register. an access of this register will clear the cpu interrupt request and the txms bit. the valid range of values that may be written to this register is $01 to $0b. since the tx buffer is 11 bytes long, any value greater than or equal to $0c written to this register will create a tx buffer overflow error and cause the mdlc to not transmit that message. figure 15-5: mdlc tx control register (mtcr) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 tc1 tc0 tc2 tc3 0 0 0 0 reset 00000000
section 15: message data link controller motorola page 101 mc68hc05v7 specification rev. 1.0 attempts to send a zero byte message body length (value of $00 written to mtcr) will also prevent the mdlc from transmitting that message. writing a value within the valid range to this register will initiate a transmission regardless of whether any new data has been loaded into the tx buffer. failure to supply new data before this register is written to will result in the mdlc transmitting whatever data happens to be in the tx buffer at the time of the write. do not write to this register while the txab bit in the mcr register is set. this register will be automatically cleared at the end of any transmission, whether it was successful, unsuccessful or aborted. 15.2.5 mdlc rx status register (mrsr) $11 this register reports the status of the mdlc receiver, including the rx buffer. all bits may be read in all modes of mcu operation. bits 4, 5, 6, and 7 will always read as zeros and can never be written to. bits 0, 1, 2, and 3 can be written to in all modes of mcu operation. 15.2.5.1 rc0,1,2,3 - receive count these bits reflect the number of bytes of the message body in the rx buffer available to the cpu. as a message is being received, the data is placed into successive locations of one of the two rx buffers. the rx buffer being filled is not visible to the programmer. a running count of the number of bytes received is kept internally. the maximum count is 11 bytes. the crc is not placed in the rx buffer and is not counted in the final indicated message length. once the message has been received error-free, the rx buffer is placed into the mcu? memory map, the mrsr is updated with the count of the number of data bytes received, a cpu interrupt request is generated if the interrupt enable (ie) bit is set and the rx message successful (rxms) bit will be set in the msr. when the programmer has finished analyzing the received message, a write to this register will signal to the mdlc that the programmer no longer needs the contents of the rx buffer. figure 15-6: mdlc rx status register (mrsr) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 rc1 rc0 rc2 rc3 0 0 0 0 reset 00000000
motorola section 15: message data link controller page 102 mc68hc05v7 specification rev. 1.0 the rx buffer will then be released back to the mdlc. if another message is available in the second rx buffer at this time, the new message will then be made available to the cpu. following a write to the mrsr to release the rx buffer, this register should not be accessed again until the rxms bit is again verified to be set. this procedure will ensure that the mrsr value does not change while it is being accessed by the cpu. if, while performing the above operations, another message begins to arrive then the second message will be placed in a duplicate rx buffer. the mdlc will always present the oldest available message to the programmer, therefore only one rx buffer appears in the memory map while the other one is filled with a newer message. if both rx buffers are filled when a third new message arrives, the third message will be ignored and the prior messages within the rx buffers will not be affected.
section 15: message data link controller motorola page 103 mc68hc05v7 specification rev. 1.0 15.3 mdlc rx/tx buffers the rx and tx buffers provide the interface between the cpu interface and the protocol handler. they provide buffering of data being sent and received, reducing the frequency of interrupts to the cpu. please refer to the mcu memory map for details on the starting and ending addresses of these buffers within the overall memory map. 15.3.1 outline during all modes of mcu operation, the rx and tx buffers are mapped as registers. memory mapping these buffers requires the mdlc to supply the user with a count of the number of bytes in each received message and allows the user to tell the mdlc the length of a message to be transmitted. access arbitration is simplified by the following rules: the user must not read the rx buffer until the mdlc signals that an entire message has been received (receive message successful bit (rxms) in the mdlc status register (msr) is set). the user returns the rx buffer resource to the mdlc by writing any value to the mdlc receive status register (mrsr). the user must not write to the tx buffer after the mdlc has been told to transmit the message (length of message has been written to the mdlc transmit control register (mtcr)). the user must wait until the mdlc has sent the message (indicated by a cpu interrupt request and the transmit message successful (txms) bit being set), or the message has been aborted (transmit abort bit (txab) in the mdlc control register (mcr) is toggled) before reloading the tx buffer. physical interface to cpu protocol handler mux interface cpu interface rx/tx buffers to j1850 bus mdlc
motorola section 15: message data link controller page 104 mc68hc05v7 specification rev. 1.0 the mdlc has three 11 byte buffer arrays. the transmit circuitry uses a single tx buffer, that for certain periods of time may have either the cpu or the mdlc access "locked out". the receiver has two rx buffers but only one can appear in the mcu memory map at a time. the cpu will have access to whichever rx buffer was filled the earliest. while the cpu is reading data from one rx buffer, the mdlc may place incoming data into the other rx buffer. when the cpu writes to the mrsr register, the rx buffer which the cpu had access to is "given back" to the mdlc making it available for another incoming message. the mdlc tx buffer is writable by the cpu at all times but it is not readable. a read of the tx buffer will result in an unknown value. the rx buffers can be read by the cpu at anytime. however, writes to the rx buffer will not have an effect on the buffer? content. note: the contents of the tx buffer are not guaranteed to remain intact following a transmission so the tx buffer should be completely reloaded for each new message to be sent.
section 15: message data link controller motorola page 105 mc68hc05v7 specification rev. 1.0 15.3.2 rx buffers the rx buffers consist of two 11-byte arrays, with 8 bits per byte. only one message may occupy each rx buffer array at any time. each rx buffer array has an internal register (the ?x buffer pointer? associated with it in which the length of the message body is recorded. following a reset, the mdlc has "possession" of the two empty rx buffers and their associated rx buffer pointers are both reset to zero. neither rx buffer appears in the cpu memory map at this time, attempts to read them will return undefined data. as each data byte of an incoming message is received by the mdlc, it is placed into the next available entry of one of the rx buffers and the rx buffer pointer is incremented. this continues until the end of the message is detected or an error occurs. figure 15-7: mdlc rx/tx buffers outline rx buffer array #1 rx buffer array #2 11 bytes 11 bytes 11 bytes mrsr mrsr mtcr mux mux mdlc rx logic mdlc tx logic to cpu from cpu mdlc automatically toggles multiplexer (mux) when one buffer is full. write to mrsr "gives back" buffer indicates active path tx buffer array to mdlc for rx. write to mtcr "gives back" buffer to mdlc for tx.
motorola section 15: message data link controller page 106 mc68hc05v7 specification rev. 1.0 if the received message is verified as error-free then the crc is discarded, the filled rx buffer and the final value of the rx buffer pointer are placed into the cpu memory map, the received message successfully (rxms) bit in the mdlc status register (msr) is set, a cpu interrupt request is made (if interrupts are enabled) and the other rx buffer and its pointer are readied for reception of the next message by the mdlc. the cpu may now randomly read the rx buffer. the first data byte received will be located in the lowest address entry of the rx buffer. the rest of the message is located in contiguous ascending address entries up to the last data byte received, which will be located in the n th entry, where ??is the final value of the rx buffer pointer which now appears in the mdlc rx status register (mrsr). as long as the cpu has possession of this rx buffer, the mdlc will have possession of the other rx buffer and can concurrently receive a second message without conflict with, or intervention by, the cpu. once the cpu has finished with the contents of the rx buffer, it may be "given back" to the mdlc by writing any value to the mrsr register. the above sequence is then repeated as long as normal data reception takes place. if the cpu is unable to return an rx buffer and the second rx buffer becomes filled and a further new message arrives from the j1850 bus then the new message will be ignored by the mdlc until an rx buffer becomes available to receive new data. if any type of reception error is detected by the mdlc as a message is being received from the j1850 bus, the internal rx buffer pointer will be reset to zero, effectively flushing the data received so far, and the mdlc will ignore the rest of the message. when this occurs the mdlc will not generate a cpu interrupt request and will silently wait for the next valid sof symbol. this will also happen if a message received from the j1850 bus is longer than 12 bytes (including crc byte), and the receive block mode (rxbm) bit is not set. in both cases, when the internal rx buffer pointer is reset to zero, the associated rx buffer array bytes will not be cleared or changed. if a message received from the j1850 bus is longer than 12 bytes (including crc byte), and the receive block mode (rxbm) bit is set then reception of the message will be continued into the next available rx buffer. this will repeat until the end of the message is detected, at which time the residual data bytes will remain in the last rx buffer to be filled. 15.3.3 tx buffer the tx buffer consists of one 11-byte array, with 8 bits per byte. only one message may occupy the tx buffer at any time. the tx buffer array has an internal register (the ?x buffer pointer? associated with it in which the length of the message body is stored. following a reset, the cpu has "possession" of the empty tx buffer and its associated tx buffer pointer is reset to zero. the tx buffer appears in the cpu memory map at this time, where the cpu may randomly access it. the first data byte of the message to be sent must be placed in the lowest address entry of the tx buffer. the rest of the message must be placed in contiguous ascending address entries up to the last data byte to be sent, which is located in the n th entry, where ??is the length of the message body to be sent.
section 15: message data link controller motorola page 107 mc68hc05v7 specification rev. 1.0 as long as the cpu has possession of the tx buffer, the mdlc cannot transmit. once the cpu has finished with the contents of the tx buffer, it may be "given back" to the mdlc by writing the message body length ??to the mdlc tx control register (mtcr). starting from the first entry of the tx buffer, the mdlc fetches each data byte from a filled entry of the tx buffer, the tx buffer pointer is incremented and the mdlc attempts to transmit the data byte onto the j1850 bus. this continues until the last byte of the message body has been fetched, arbitration is lost or an error occurs. if the transmitted message is sent error-free then a crc is appended, the filled tx buffer is given back to the cpu, the transmitted message successfully (txms) bit in the mdlc status register (msr) is set, and a cpu interrupt request is made (if interrupts are enabled). this sequence is then repeated as long as normal data transmission takes place. if any type of transmission error is detected by the mdlc as a message is being transmitted onto the j1850 bus, the internal tx buffer pointer will be reset to zero, effectively flushing the data to be sent, and the mdlc will automatically abort transmission. when this occurs the mdlc will not generate a cpu interrupt request and will silently wait for the next write to the mtcr register. if a loss of arbitration occurs while the mdlc is attempting to transmit a message, the mdlc will immediately halt transmission and become a receiver. as soon as an idle bus condition is detected, the mdlc will again attempt to transmit the message onto the multiplex bus. this automatic retry will continue until the message is transmitted successfully, an error is detected during transmission, or the txab bit is set by the cpu. since the tx buffer is 11 bytes long, any value greater than or equal to $0c written to the mtcr register will create a tx buffer overflow error and cause the mdlc to not transmit that message. attempts to send a zero byte message body length (value of $00 written to mtcr) will also cause the mdlc to not transmit that message. at the end of a transmission, successful, unsuccessful or aborted, the mtcr register is automatically cleared. if interrupts are enabled, the programmer should not poll the mtcr register to detect this action since each access will clear the txms bit in the msr register! instead, since the mdlc receives every message that it sends, the programmer should check that each message that is attempted to be sent is received back within some acceptable amount of time before attempting to send another message. failure to receive back a message that has been sent in a timely fashion might indicate that some network fault exists.
motorola section 15: message data link controller page 108 mc68hc05v7 specification rev. 1.0 15.4 mdlc protocol handler the protocol handler is responsible for framing, collision detection, arbitration, crc generation/checking, and error detection. the protocol handler conforms to sae j1850 - class b data communications network interface. 15.4.1 outline the protocol handler contains three main blocks: the state machine, rx shift register and tx shift register, as shown below. each block will now be described in more detail. 15.4.2 rx & tx shift registers the rx shift register gathers received serial data bits from the j1850 bus and makes them available in parallel form to the rx buffer. the tx shift register takes data, in parallel form, from the tx buffer and presents it serially to the state machine so that it can be transmitted onto the j1850 bus. physical interface to cpu protocol handler mux interface cpu interface rx/tx buffers to j1850 bus mdlc rx shift register figure 15-8: mdlc protocol handler outline to cpu interface & rx/tx buffers state machine to mux interface rx data tx data control 8 tx shift register txp rxp control 8
section 15: message data link controller motorola page 109 mc68hc05v7 specification rev. 1.0 15.4.3 state machine all of the functions associated with performing the protocol are executed or controlled by the state machine. the state machine is responsible for framing, collision detection, arbitration, crc generation/checking, and error detection. the following sections describe the mdlc? actions in a variety of situations. 15.4.3.1 in-frame response the mdlc does not support the in-frame response (ifr) feature of j1850. if the mdlc receives an ifr, it will ignore the response ( not placing it in an rx buffer) and wait for the end of frame (eof) symbol. 15.4.3.2 4x speed mode the mdlc can exist on the same j1850 bus as modules which use a special 4x mode of j1850 vpw operation. the mdlc treats 4x mode messages as noise and ignores them. the mdlc will wait for a valid sof or break at 10.4 kbps to resume normal operation. 15.4.3.3 block mode while the mdlc can only transmit a maximum of 12 bytes (including crc byte) in a given message, it has the ability to receive a message of unlimited length. like 4x mode, the programmer will have to determine from a received message that block mode is to be enabled. the programmer then sets the ?eceive block message?(rxbm) bit in the mdlc control register (mcr) to indicate to the mdlc that the following message will be longer than 12 bytes and not to treat it as a message over length error. 15.4.3.4 arbitration arbitration is performed by the mdlc simply by comparing the data being received from the j1850 bus with the data being transmitted. this is done by latching the data being transmitted into a comparator, where it is compared with the data being received from the j1850 bus. if a valid data bit is received which has a higher priority over what was transmitted (0 over 1), arbitration is then lost, and the transmitter stops transmitting until a valid eof symbol is received from the j1850 bus. see 15.5.5 message arbitration for more information. if an invalid bit or a symbol in a non-byte boundary is detected, the transmitter will also stop transmitting. in vpw, an active signal will always dominate a passive one, and a shorter passive symbol will dominate a longer passive symbol. this ensures that a logic zero will dominate a logic one, and the message with the highest priority (lowest value) will win arbitration. see 15.5.5 message arbitration for more details. 15.4.3.5 j1850 bus errors the mdlc detects several types of transmit and receive errors which can occur during the transmission of a message onto the j1850 bus.
motorola section 15: message data link controller page 110 mc68hc05v7 specification rev. 1.0 if the mdlc is transmitting a message and the message received contains invalid bits, or framing symbols on non-byte boundaries, this constitutes a transmission error. when a transmission error is detected, the mdlc will immediately cease transmitting. if the mdlc is receiving a message and it detects an error during the message, the message is discarded. no message with an error contained in it is passed to the cpu and no error status information is available. 15.4.3.5.1 crc error a crc error is detected when the data bytes and crc byte of a received message are processed, and the crc calculation result is not equal to $c4. the crc code should detect any single and 2 bit errors, as well as all 8 bit burst errors, and almost all other types of errors. 15.4.3.5.2 bit format error a bit format error is detected when an abnormal (invalid) bit is detected in a message being received from the j1850 bus. however, if the mdlc is transmitting when this happens, it will be treated as a loss of arbitration rather than a transmitter error and the automatic retry mechanism will apply. 15.4.3.5.3 message format error a message format error is detected if an eod or eof symbol is detected on a non-byte boundary from the j1850 bus. 15.4.3.5.4 bus fault if a bus fault occurs, the response of the mdlc will depend upon the type of bus fault. if the bus is shorted to v batt , the mdlc will wait for the bus to fall to a passive state before it will attempt to transmit a message. as long as the short remains, the mdlc will never attempt to transmit a message onto the j1850 bus. if the bus is shorted to ground, the mdlc will see an idle bus, begin to transmit the message, and then detect a transmission error, since the short to ground would not allow the bus to be driven to the dominant state. the mdlc will abort that transmission and wait for the next cpu command to transmit. in any case, if the bus fault is temporary, as soon as the fault is cleared, the mdlc will resume normal operation. if the bus fault is permanent, it may result in permanent loss of communication on the j1850 bus. 15.4.3.5.5 message under length error any message received by the mdlc must be at least two bytes long. since the mdlc does not have message filtering, these two bytes could just be one data byte and a crc byte. any messages received with less than the minimum number of bytes will be discarded by the mdlc. 15.4.3.5.6 message over length error a message over length error is detected when a message being received exceeds the maximum length allowed for a message on the j1850 bus. if the receive block mode (rxbm) bit is not set, the maximum received length from sof to the eod is 12 bytes
section 15: message data link controller motorola page 111 mc68hc05v7 specification rev. 1.0 including the crc byte. any messages received with more than the maximum number of bytes will be discarded by the mdlc. 15.4.3.5.7 invalid active level if the mdlc transmits an active symbol but senses that the bus remains active longer than 163 us, then the mdlc will stop transmitting. the mdlc will treat this invalid active level just like a received break symbol. the mdlc will try to transmit the message again after an idle bus is detected. 15.4.3.5.8 break - break any mdlc transmitting at the time a break is detected will treat the break as if a loss of arbitration had occurred, and halt transmission. the mdlc will then retry to transmit the message. if while receiving a message the mdlc detects a break symbol, it will treat the break as a reception error and clear the current rx buffer pointer. table 15-3: mdlc j1850 bus error summary error condition mdlc function bus short to v batt . the mdlc will not transmit until the bus is idle. bus short to gnd. the mdlc will try only once to send the message. no interrupt will be generated. mdlc transmits but receives invalid bits (noise). the mdlc will abort transmission immediately. no interrupt will be generated. mdlc receives invalid bit. the mdlc will reset the rx buffer pointer and wait for the next valid sof. no interrupt will be generated. mdlc receives message framing error. the mdlc will reset the rx buffer pointer and wait for the next valid sof. no interrupt will be generated. mdlc receives under length or over length message. the mdlc will reset the rx buffer pointer and wait for the next valid sof. no interrupt will be generated. mdlc receives invalid crc the mdlc will reset the rx buffer pointer and wait for the next valid sof. no interrupt will be generated. mdlc receives break symbol the mdlc will reset the rx buffer pointer and wait for the next valid sof. no interrupt will be generated. mdlc sends an eod but receives an active symbol. the mdlc will reset the rx buffer pointer and try to resend that message after an idle bus.
motorola section 15: message data link controller page 112 mc68hc05v7 specification rev. 1.0 15.5 mdlc mux interface the mux interface is responsible for bit encoding/decoding and digital noise filtering between the protocol handler and the physical interface. 15.5.1 rx digital filter the receiver section of the mdlc includes a digital low pass filter to remove narrow noise pulses from the incoming message. an outline of the digital filter is shown below. physical interface to cpu protocol handler mux interface cpu interface rx/tx buffers to j1850 bus mdlc figure 15-9: mdlc rx digital filter block 4-bit up/down counter data latch up/down = 15 s q filtered rx data out mux interface clock input sync dq rx data from physical interface (rxp) = 0 r
section 15: message data link controller motorola page 113 mc68hc05v7 specification rev. 1.0 15.5.1.1 operation the clock for the digital filter is provided by the mux interface clock. at each positive edge of the clock signal, the current state of the receiver physical interface (rxp) signal is sampled. the rxp signal state is used to determine whether the counter should increment or decrement at the next negative edge of the clock signal. the counter will increment if the input data sample is high but decrement if the input sample is low. the counter will thus progress up towards ?5?if, on average, the rxp signal remains high or progress down towards ??if, on average, the rxp signal remains low. when the counter eventually reaches the value ?5? the digital filter decides that the condition of the rxp signal is at a stable logic level one and the data latch is set, causing the filtered rx data signal to become a logic level one. furthermore, the counter is prevented from overflowing and can only be decremented from this state. alternatively, should the counter eventually reach the value ?? the digital filter decides that the condition of the rxp signal is at a stable logic level zero and the data latch is reset, causing the filtered rx data signal to become a logic level zero. furthermore, the counter is prevented from underflowing and can only be incremented from this state. the data latch will retain its value until the counter next reaches the opposite end point, signifying a definite transition of the rxp signal. 15.5.1.2 performance the performance of the digital filter is best described in the time domain rather than the frequency domain. if the level of the rxp signal transitions, then there will be a delay before that transition appears at the filtered rx data output signal. this delay will be between 15 and 16 clock periods, depending on where the transition occurs with respect to the sampling points. this ?ilter delay?must be taken into account when performing message arbitration. for example, if the frequency of the mux interface clock (f mdlc ) is 1.0486mhz, then the period (t mdlc ) is 954ns and the maximum filter delay in the absence of noise will be 15.259us. the effect of random noise on the rxp signal depends on the characteristics of the noise itself. narrow noise pulses on the rxp signal will be completely ignored if they are shorter than the filter delay. this provides a degree of low pass filtering. if noise occurs during a symbol transition, the detection of that transition may be delayed by an amount equal to the length of the noise burst. this is just a reflection of the uncertainty of where the transition is truly occurring within the noise. noise pulses that are wider than the filter delay, but narrower than the shortest allowable symbol length will be detected by the next stage of the mdlc? receiver as an invalid symbol. noise pulses that are longer than the shortest allowable symbol length will normally be detected as an invalid symbol or as invalid data when the frame? crc is checked.
motorola section 15: message data link controller page 114 mc68hc05v7 specification rev. 1.0 15.5.2 j1850 frame format all messages transmitted on the j1850 bus are structured using the format: each message has a maximum length of 12 bytes (excluding sof, eod, nb and eof). 15.5.2.1 sof - start of frame symbol all messages transmitted onto the j1850 bus must begin with an sof symbol. this indicates to any listeners on the j1850 bus the start of a new message transmission. the sof symbol is not used in the crc calculation. 15.5.2.2 data - in message data bytes the data bytes contained in the message include the message header bytes and any actual data being transmitted to the receiving node. the mdlc can be used to transmit messages using any of the three header formats outlined in the sae j1850 document. however, the mdlc does not utilize the ifr, header type or functional/physical addressing bits defined in the 1st byte of the 3-byte consolidated header message format. see sae j1850 - class b data communications network interface , for more information about 1- and 3-byte headers. messages transmitted by the mdlc onto the j1850 bus must contain at least one data byte, and therefore can be as short as one data byte and one crc byte. each data byte in the message is 8 bits in length, transmitted msb to lsb. 15.5.2.3 crc - cyclical redundancy check byte this byte is used by the receiver(s) of each message to determine if any errors have occurred during the transmission of the message. the mdlc calculates the crc byte and appends it onto any messages transmitted onto the j1850 bus, and also performs crc detection on any messages it receives from the j1850 bus. crc generation uses the divisor polynomial x 8 +x 4 +x 3 +x 2 +1. the remainder polynomial is initially set to all ones, and then each byte in the message after the sof symbol is serially processed through the crc generation circuitry. the one? complement of the remainder then becomes the 8-bit crc byte, which is appended to the message after the data bytes, in msb to lsb order. when receiving a message, the mdlc uses the same divisor polynomial. all data bytes, excluding the sof and eod symbols, but including the crc byte, are used to check the crc. if the message is error free, the remainder polynomial will equal x 7 +x 6 +x 2 ($c4), regardless of the data contained in the message. if the calculated crc does not equal $c4, the mdlc will recognize this as a crc error, and will discard the message, not informing the cpu of the failure. sof e o d eof data n crc ifr i f s idle idle figure 15-10: j1850 bus message format (vpw) optional data 1 data 0
section 15: message data link controller motorola page 115 mc68hc05v7 specification rev. 1.0 15.5.2.4 eod - end of data symbol the eod symbol is a short passive period on the j1850 bus used to signify to any recipients of a message that the transmission by the originator has completed. 15.5.2.5 ifr - in frame response bytes the ifr section of the j1850 message format is optional. the mdlc does not support this option. the mdlc will not transmit an ifr under any circumstances. if an ifr is received from another node, the mdlc will ignore this part of the message and wait for the eof symbol before resuming normal operation. 15.5.2.6 eof - end of frame symbol this symbol is a passive period on the j1850 bus, longer than an eod symbol, which signifies the end of a message. since an eof symbol is longer than an eod symbol, if no response is transmitted after an eod symbol, it becomes an eof, and the message is assumed to be completed. 15.5.2.7 ifs - inter-frame separation symbol the ifs symbol is a passive period on the j1850 bus that allows proper synchronization between nodes during continuous message transmission. the ifs symbol is transmitted by a node following the completion of the eof period. when the last byte of a message has been transmitted onto the j1850 bus, and the eof symbol time has expired, all nodes must then wait for the ifs symbol time to expire before transmitting an sof, marking the beginning of another message. however, if the mdlc is waiting for the ifs period to expire before beginning a transmission and a rising edge is detected before the ifs time has expired, it must internally synchronize to that edge. if a write to the mtcr register (initiate transmission) occurred on or before 104 t mdlc from the received rising edge, then the mdlc will transmit and arbitrate for the bus. if a cpu write to the mtcr register occurred after 104 t mdlc from the detection of the rising edge, then the mdlc will not transmit, but will wait for the next ifs period to expire before attempting to transmit the message. a rising edge may occur during the ifs period because of varying clock tolerances and loading of the j1850 bus, causing different nodes to observe the completion of the ifs period at different times. receivers must synchronize to any sof occurring during an ifs period to allow for individual clock tolerances. 15.5.2.8 break - break any mdlc transmitting at the time a break is detected will treat the break as if a loss of arbitration had occurred, and halt transmission. the mdlc cannot transmit a break symbol. if while receiving a message the mdlc detects a break symbol, it will treat the break as a reception error and clear any partially received message from the rx buffer. 15.5.2.9 idle bus an idle condition exists on the bus during any passive period after expiration of the ifs period. any node sensing an idle bus condition can begin transmission immediately.
motorola section 15: message data link controller page 116 mc68hc05v7 specification rev. 1.0 15.5.3 j1850 vpw symbols variable pulse width modulation (vpw) is an encoding technique in which each bit is defined by the time between successive transitions, and by the level of the bus between transitions, active or passive. active and passive bits are used alternately. each logic one or logic zero contains a single transition, and can be at either the active or passive level and one of two lengths, either 64 m s or 128 m s (t nom at 10.4 kbps baud rate), depending upon the encoding of the previous bit. the sof, eod, eof and ifs symbols will always be encoded at an assigned level and length. see figure 15-11: j1850 vpw symbols each message will begin with an sof symbol, an active symbol, and therefore each data byte (including the crc byte) will begin with a passive bit, regardless of whether it is a logic one or a logic zero. all vpw bit lengths stated in the following descriptions are typical values at a 10.4 kbps bit rate. 128 m s active passive 64 m s or logic "0" 128 m s active passive 64 m s or logic "1" 200 m s active passive start of frame 200 m s end of data 280 m s active passive end of frame 3 280 m s break (a) (b) (c) (d) (e) (f) figure 15-11 : j1850 vpw symbols
section 15: message data link controller motorola page 117 mc68hc05v7 specification rev. 1.0 15.5.3.1 logic "0" a logic zero is defined as either an active to passive transition followed by a passive period 64 m s in length, or a passive to active transition followed by an active period 128 m s in length (figure 15-11(a)). 15.5.3.2 logic "1" a logic one is defined as either an active to passive transition followed by a passive period 128 m s in length, or a passive to active transition followed by an active period 64 m s in length (figure 15-11(b)). 15.5.3.3 sof - start of frame symbol the sof symbol is defined as a passive to active transition followed by an active period 200 m s in length (figure 15-11(c)). this allows the data bytes that follow the sof symbol to begin with a passive bit, regardless of whether it is a logic one or a logic zero. 15.5.3.4 eod - end of data symbol the eod symbol is defined as an active to passive transition followed by a passive period 200 m s in length (figure 15-11(d)). 15.5.3.5 eof - end of frame symbol the eof symbol is defined as an active to passive transition followed by a passive period of at least 280 m s in length (figure 15-11(e)). if there is no ifr byte transmitted after an eod symbol is transmitted, after another 80 m s the eod becomes an eof, indicating the completion of the message. 15.5.3.6 ifs - inter-frame separation symbol the ifs symbol is defined as a passive period 300 m s in length. the ifs symbol contains no transition, since when used it always follows an eof symbol. 15.5.3.7 break - break signal the break signal is defined as a passive to active transition followed by an active period of at least 280 m s (figure 15-11(f)). 15.5.4 j1850 vpw valid/invalid bits & symbols the timing tolerances for receiving data bits and symbols from the j1850 bus have been defined to allow for variations in oscillator frequencies. in many cases the maximum time allowed to define a data bit or symbol is equal to the minimum time allowed to define another data bit or symbol. since the minimum resolution of the mdlc for determining what symbol is being received is equal to a single period of the mux interface clock (t mdlc ), an apparent separation in these maximum time/minimum time concurrences equal to one cycle of t mdlc occurs. this one clock resolution allows the mdlc to properly differentiate between the different bits and symbols, without reducing the valid window for receiving bits and symbols from transmitters onto the j1850 bus having varying oscillator frequencies.
motorola section 15: message data link controller page 118 mc68hc05v7 specification rev. 1.0 in vpw bit encoding, the tolerances for the both passive and active data bits and symbols are defined with no gaps between definitions. for example, the maximum length of a passive logic zero is equal to the minimum length of a passive logic one, and the maximum length of an active logic zero is equal to the minimum length of a valid sof symbol 15.5.4.1 invalid passive bit if the passive to active transition beginning the next data bit or symbol occurs between the active to passive transition beginning the current data bit or symbol and a , the current bit would be invalid. see figure 15-12(1). 15.5.4.2 valid passive logic zero if the passive to active transition beginning the next data bit or symbol occurs between a and b , the current bit would be considered a logic zero. see figure 15-12(2). 15.5.4.3 valid passive logic one if the passive to active transition beginning the next data bit or symbol occurs between b and c , the current bit would be considered a logic one. see figure 15-12(3). 15.5.4.4 valid eod symbol if the passive to active transition beginning the next data bit or symbol occurs between c and d , the current symbol would be considered a valid eod symbol. see figure 15-12(4). a bc b a (1) invalid passive (2) valid passive (3) valid passive 64 m s 128 m s figure 15-12 : j1850 vpw passive symbols cd (4) valid eod symbol logic one bit logic zero 200 m s active passive active passive active passive active passive
section 15: message data link controller motorola page 119 mc68hc05v7 specification rev. 1.0 15.5.4.5 valid eof & ifs symbol if the passive to active transition beginning the sof symbol of the next message occurs between a and b , the current symbol will be considered a valid eof symbol. if the passive to active transition beginning the sof symbol of the next message occurs between c and d , the current symbol will be considered a valid eof symbol followed by a valid ifs symbol. all nodes must wait until a valid ifs symbol time has expired before beginning transmission. however, due to variations in clock frequencies and bus loading, some nodes may recognize a valid ifs symbol before others, and immediately begin transmitting. therefore, anytime a node waiting to transmit detects a passive to active transition once a valid eof has been detected, it should immediately begin transmission, initiating the arbitration process. see figure 15-13(1&2). 15.5.4.6 idle bus if the passive to active transition beginning the sof symbol of the next message does not occur before d, the bus is considered to be idle, and any node wishing to transmit a message may do so immediately. cd (2) valid eof+ ifs symbol 280 m s 580 m s ab (1) valid eof symbol figure 15-13 : j1850 vpw eof and ifs symbols active passive active passive
motorola section 15: message data link controller page 120 mc68hc05v7 specification rev. 1.0 15.5.4.7 invalid active bit if the active to passive transition beginning the next data bit or symbol occurs between the passive to active transition beginning the current data bit or symbol and a , the current bit would be invalid. see figure 15-14(1). 15.5.4.8 valid active logic one if the active to passive transition beginning the next data bit or symbol occurs between a and b , the current bit would be considered a logic one. see figure 15-14(2). 15.5.4.9 valid active logic zero if the active to passive transition beginning the next data bit or symbol occurs between b and c , the current bit would be considered a logic zero. see figure 15-14(3). figure 15-14 : j1850 vpw active symbols a bc b a (1) invalid active (2) valid active (3) valid active 64 m s 128 m s d bit logic one logic zero (4) valid sof symbol 200 m s de (5) valid break symbol c 280 m s
section 15: message data link controller motorola page 121 mc68hc05v7 specification rev. 1.0 15.5.4.10 valid sof symbol if the active to passive transition beginning the next data bit or symbol occurs between c and d , the current symbol would be considered a valid sof symbol. see figure 15-14(4). 15.5.4.11 valid break symbol if the next active to passive transition does not occur until after d , the current symbol will be considered a valid break symbol. following the break symbol, an ifs period must be observed, after which normal communication can resume on the j1805 bus. see figure 15-14(5). 15.5.5 message arbitration message arbitration on the j1850 bus is accomplished in a non-destructive manner, allowing the message with the highest priority to be transmitted, while any transmitters which lose arbitration simply stop transmitting and wait for an idle bus to begin transmitting again. if the mdlc wishes to transmit onto the j1850 bus, but detects that another message is in progress, it must wait until the bus is idle. however, if multiple nodes begin to transmit in the same synchronization window, message arbitration will occur beginning with the first bit after the sof symbol and continue with each bit thereafter. the vpw symbols and j1850 bus electrical characteristics are carefully chosen so that a logic zero (active or passive type) will always dominate over a logic one (active or passive type) simultaneously transmitted. hence logic zeroes are said to be ?ominant?and logic ones are said to be ?ecessive? whenever a node detects a dominant bit when it transmits a recessive bit, it loses arbitration, and immediately stops transmitting. this is known as ?itwise arbitration? figure 15-15: j1850 vpw bitwise arbitration transmitter a transmitter b j1850 bus sof data bit 1 data bit 4 data bit 5 "0" transmitter a detects an active state on the bus, and stops transmitting transmitter b wins passive active passive active passive active "0" "0" "1" "1" "1" data bit 2 "1" "1" "1" data bit 3 "0" "0" "0" "0" "1" arbitration and continues transmitting
motorola section 15: message data link controller page 122 mc68hc05v7 specification rev. 1.0 during arbitration, or even throughout the message being transmitted, when an opposite bit is detected, transmission is immediately stopped unless it occurs on the 8th bit of a byte. in this case the mdlc will automatically append up to two extra 1 bits and then stop transmitting. these two extra bits will be arbitrated normally and thus will not interfere with another message. the second 1 bit will not be sent if the first loses arbitration. if the mdlc has lost arbitration to another valid message then the two extra ones will not corrupt the current message. however, if the mdlc has lost arbitration due to noise on the bus, then the two extra ones will ensure that the current message will be detected and ignored as a noise-corrupted message. since a "0" dominates a "1", the message with the lowest value will have the highest priority, and will always win arbitration, i.e. a message with priority 000 will win arbitration over a message with priority 001. this method of arbitration will work no matter how many bits of priority encoding are contained in the message. if the mdlc loses arbitration during the transmission of a message, it will attempt to retransmit as soon as a valid eof is detected on the j1850 bus. the mdlc will attempt to retransmit the message indefinitely, as long as messages with higher priorities continue to win arbitration. the only way to stop transmission retry due to loss of arbitration is to abort the transmission by setting the tx abort (txab) bit in the mdlc control register. this will reset the internal tx buffer pointer and halt transmission.
section 15: message data link controller motorola page 123 mc68hc05v7 specification rev. 1.0 15.6 mdlc physical interface all analog functions involved in transmitting and receiving from the j1850 bus are performed by the physical interface. the physical interface serves to buffer the incoming messages, wave-shape the messages being transmitted, and protect the mdlc from transients occurring on the j1850 bus. 15.6.1 outline the receiver analog comparator and transmitter drivers are included in the mdlc physical interface and together are referred to as the "transceiver". the transceiver provides a waveshaped 7v bus waveform in response to a timed logic signal from the mux interface. the transceiver actively drives the bus high, and passively lets an rc network pull the bus low. in order to achieve the 7v level necessary for the bus signal, the transceiver uses a battery supply (v batt ) which is nominally 12v. the transceiver also receives bus waveforms and provides the mux interface with unfiltered input data a low power mode of operation is automatically entered if the cpu executes a stop or wait instruction. in the event that ground is lost, the transceiver senses this condition and releases the bus by switching the load pin to a high impedance instead of a low impedance to ground.the transceiver also protects the mdlc by not passing on any standard disruptive or non- disruptive signals seen on the bus to the rest of the mdlc. the physical interface contains its own power-on reset circuit that is used to reset its control circuitry whenever a power-on condition is detected. physical interface to cpu protocol handler mux interface cpu interface rx/tx buffers to j1850 bus mdlc
motorola section 15: message data link controller page 124 mc68hc05v7 specification rev. 1.0 see figure 15-16: mdlc physical interface outline for an example mechanization for interfacing the mdlc module to the j1850 multiplex bus physical layer. although this example mechanization is designed to provide some transient protection beyond what the mdlc module can withstand directly, the user should ensure that their circuit design meets the transient protection requirements of their application.
section 15: message data link controller motorola page 125 mc68hc05v7 specification rev. 1.0 figure 15-16 : mdlc physical interface outline txp rxp driver bus physical interface sleep/wake prst v batt load r1 l1 waveshaper c1 sleep & wake rx comparator control + - v ref rext1 rext2 v dd v ssd to v dd +5v voltage references & control 0.1 m f p6ke15a 0.1 m f 0v +12v j1850 bus 31.6 k w 1% 24.9 k w 1% mdlc use r1 c1 l1 1st node in system 1.5k w 1% 3300pf/2700pf* tdk nl322522t-470j-3 (surface) tdk sp0203-470k-7 (leaded) all other nodes 10.7k w 1% 470pf/220pf* tdk nl322522t-470j-3 (surface) tdk sp0203-470k-7 (leaded) all circuit board grounds ( ) should be tied to a single point on the circuit board. the chassis ground ( ) should be tied to a single point on the chassis as close to the bus connector as possible. the l1,c1 filter should be located as close to the bus connector as possible. r1, rext1, rext2 and decoupling capacitors should be located as close as possible to the mdlc transient protection circuits are optional and are only examples of how a protection scheme might be implemented, these devices may not be sufficient for all applications and under all circumstances. p6ke30a 1n5822 example v batt transient protection v cca tsma16a(surface) locate close to connector example transient/esd protection p4ka16a(leaded) both notes: * values account for load contributions by protection devices 47 m h keep lead lengths to a minimum on leaded devices
motorola section 15: message data link controller page 126 mc68hc05v7 specification rev. 1.0 15.6.2 mux interface signals there are five signals which pass between the physical interface and the mux interface section of the mdlc as shown in figure 15-16: mdlc physical interface outline . these signals are now described. 15.6.2.1 sleep/wake this input signal is used to control the power consumption of the physical interface transmitter. when driven high by the mux interface, the transmitter will enter a low power consumption sleep mode. this will happen whenever the cpu executes a stop or wait instruction. the transmitter is not capable of transmitting while it is in the sleep mode. when driven low by the mux interface, the transmitter will wake-up ?and become capable of transmitting messages. this will happen when the mdlc enters the run mode. 15.6.2.2 wake this input signal is used to exit the low power consumption mode of the physical interface transmitter. the mux interface will drive this signal high and then low to notify the transmitter to wake up from sleep mode. this will happen whenever the transmitter is in the sleep mode and a passive to active transition occurs on the j1850 bus, causing the rxp signal to transition from low to high. 15.6.2.3 prst this is the reset signal input to the physical interface. this signal is normally low and the mux interface will drive this signal high to reset the physical interface control circuits. 15.6.2.4 txp this input signal represents the digital serial transmit data from the mux interface to the physical interface. when sending a passive phase, this signal will be driven low . when sending an active phase, this signal will be driven high . 15.6.2.5 rxp this output signal represents the digital serial receive data from the physical interface to the mux interface. when receiving an active phase, this signal will be driven high. when receiving a passive phase this signal will be driven low .
section 15: message data link controller motorola page 127 mc68hc05v7 specification rev. 1.0 15.6.3 pins there are seven pins associated with the mdlc module. figure 15-16: mdlc physical interface outline gives an example mechanization. a brief description of each pin follows. 15.6.3.1 rext1, rext2 these are external biasing resistor tie points for transmitter waveshaping and they must be referenced to the v dd pin through lines which are as low impedance and low noise as possible to ensure consistent operation. 15.6.3.2 bus this is the half-duplex data line for j1850 communications. 15.6.3.3 load this is the switched ground connection for the j1850 bus, via an rc load. 15.6.3.4 v batt this is the source for battery voltage for the mdlc. this power supply pin must be protected against transient and fault conditions. to protect against loss of battery, a low voltage protect circuit within the transceiver disables drive from the bus pin to prevent erroneous messages from being transmitted. nominal trip points are v tivb volts on v batt and v rivd volts on v cca . 15.6.3.5 v cca this is the mdlc analog transceiver power supply input and is nominally 5v. this supply must be kept as low impedance and low noise as possible. it may be supplied from a different voltage regulator source than v dd. whenever the voltage on this pin rises from zero to its nominal operating value, the physical interface detects this power-on condition and resets its control circuits. also, whenever the voltage on this pin falls below its minimum operating value, the mdlc analog circuitry will return to its reset state. 15.6.3.6 v ssa2 this is the physical interface power supply ground. this supply must be kept as low impedance and low noise as possible. it must be connected directly to the same grounding point that the main mcu v ss uses. 15.6.3.7 decoupling good supply decoupling, as close as possible to the supply pins, is absolutely essential to guarantee correct operation, minimize rfi and maximize analog performance. mdlc and non-mdlc supply lines should be kept separate to minimize interaction. emphasis should be placed on keeping supply and ground line impedances as low as possible, with preference given to ground lines if some compromise is necessitated. ground planes and wide, short, pcb traces can help significantly here. decoupling capacitors should be of low
motorola section 15: message data link controller page 128 mc68hc05v7 specification rev. 1.0 impedance construction, with regard to high frequencies, and placed as close as is physically possible to the supply pins of the mdlc. see motorola application note designing for emc with hcmos microcontrollers (an1050) for more help on this matter. 15.7 mdlc application notes 15.7.1 initialization the mcu will first write to the mdlc control register (mcr). this byte should configure the rate select bits to configure the mux interface clock to its nominal value, and set the interrupt enable bit if desired. 15.7.2 transmitting a message the mdlc is ready for loading of a new message for transmission when the txms bit in the mdlc status register (msr) is set to a 1, or had been set but was cleared by a subsequent access of the mdlc transmit control register (mtcr). the mcu will first load bytes for transmission into the tx buffer. once the data bytes have been loaded, the mcu will then write the transmit count to the mtcr register. this will command the mdlc to begin transmission on the j1850 bus at the next idle bus period. the mdlc will automatically calculate and append a crc to the last byte of the transmitted message. if the ie bit was set in the mcr register an interrupt request will be generated for the receipt of this message from the j1850 bus. the mcu should clear the interrupt by an access (read or write) to the mtcr register. the txms and rxms bits in the msr register will be set by the mdlc upon reception of this message. the txms bit is cleared by any access (read or write) of the mtcr register. the rxms bit is cleared by any access (read or write) of the mdlc receive status register (mrsr). the mdlc is now available to transmit another message. a transmitting node should verify the correct transmission of its message by waiting for the transmit message successful (txms) bit to be set in the msr register. the only way to check for incorrect transmission of a message is for the mcu to provide a time-out if the txms bit is not set in a certain length of time. this is the only way to detect the unsuccessful transmission of a message, because any received message with errors is neither stored nor indicated as received in error by the mdlc. 15.7.3 receiving a message when a complete message is received by the mdlc error-free from the sae j1850 bus, the rxms bit in the msr will be set. in addition, if the ie bit in the mcr is set, a cpu interrupt request will be generated. the rxms bit and the cpu interrupt are cleared by an access (read or write) of the mrsr register, unless a second message has also been received from the sae j1850 bus and is waiting to be retrieved. the mcu may extract received message bytes from the mdlc by reading successive rx buffer locations beginning at the lowest address location of the rx buffer. the received message bytes can be accessed any number of times, in any order, by the cpu. the cpu can determine the number of bytes to read by the receive count indicated in the mrsr
section 15: message data link controller motorola page 129 mc68hc05v7 specification rev. 1.0 register. if in block mode (rxbm bit set by mcu in mcr register) the mcu should treat the received bytes as part of an in-progress message until the mdlc clears the rxbm bit. once the received data bytes of interest to the cpu have been analyzed, the mcu must write any quantity to the mrsr register to free it for the next received message. 15.7.4 receiving a message in block mode although not a part of the sae j1850 protocol, the mdlc does allow for a special ?lock mode?of operation for the receiver only. the mdlc cannot transmit block mode messages. as far as the mdlc is concerned, a block mode message is simply a long j1850 frame that contains an indefinite number of data bytes. all of the other features of the frame remain the same, including the sof, crc and eod symbols. another node wishing to send a block mode transmission must first inform all other nodes on the network that this is about to happen. this is usually accomplished by sending a special predefined message. mdlc nodes wishing to receive the message should set the receive block mode (rxbm) bits in the mdlc control register (mcr). since the mdlc only has a finite amount of received data buffering available, the programmer must ensure that received data is moved from the rx buffers to the application memory throughout the duration of the block mode message. the mdlc aids the user by utilizing both rx buffers to buffer the arriving data bytes in block mode. as soon as one rx buffer fills, the incoming data ?pills over?into the second rx buffer, the received message successfully (rxms) bit in the mdlc status register (msr) will be set and a cpu interrupt request is generated, signalling to the user that an rx buffer must be emptied and "given back" in the same manner as explained for receiving normal messages. this alternate filling of rx buffers gives plenty of time for one rx buffer to be emptied by the user, while the other one is being filled by the mdlc. the rx buffers will continue to be alternately filled and emptied until an eod symbol, or error, is detected. throughout the reception of the block mode message, the mdlc will calculate a running crc. when an eod symbol is finally detected, the crc will be checked and, if correct, the received message successfully (rxms) bit in the mdlc status register (msr) will be set, the rxbm bit will be cleared and a cpu interrupt request will be generated. should the second rx buffer ever fill, then it will attempt to spill over into the first rx buffer which (hopefully) has been emptied in time. if not, an overflow condition is detected, both rx buffer pointers are reset (discarding the data currently held in the rx buffers), the rxbm bit will be cleared, and the mdlc will silently wait for the next normal j1850 message to be received. any other errors detected during the reception of a block mode message (for example, invalid symbols) will result in these same actions. mdlc nodes not wishing to receive a block mode message can leave the rxbm bit clear, causing all block mode messages to be completely ignored. the next normal j1850 message to appear on the bus will be automatically received as long as it contains no errors.
motorola section 15: message data link controller page 130 mc68hc05v7 specification rev. 1.0 15.7.5 mdlc stop mode this power conserving mode is automatically entered from the run mode whenever the cpu executes a stop instruction, or if the cpu executes a wait instruction and the wcm bit in the mcr register is previously set. this is the lowest power mode that the mdlc can enter. a subsequent passive to active transition on the j1850 bus will cause the mdlc to ?ake up?and generate a non-maskable cpu interrupt request. the mdlc is not guaranteed to correctly receive the message which woke it up since it may take some time for the mdlc internal operating clocks to restart and stabilize. when mdlc stop mode is entered, the analog circuitry within the transmitter will be put into a power conserving ?leep?mode. in mdlc stop mode the mdlc can neither do wave shaping nor drive any data. therefore, it is important that the programmer ensures that all transmissions are complete or aborted before putting the mdlc into mdlc stop mode. if this mode is entered while the mdlc is receiving a message, the first subsequent received edge will cause the mdlc to immediately wake up, generate a cpu interrupt request, and wait for the mdlc internal operating clocks to restart and stabilize before normal communication can resume. therefore, the mdlc is not guaranteed to correctly receive that message. 15.7.6 mdlc wait mode this power conserving mode is automatically entered from the run mode whenever the cpu executes a wait instruction and the wcm bit in the mcr register is previously clear. a subsequent successfully received message, including one that is in progress at the time that this mode is entered, will cause the mdlc to ?ake up?and generate a cpu interrupt request if the interrupt enable (ie) bit in the mcr register is previously set. this results in less of a power saving, but the mdlc is guaranteed to correctly receive the message which woke it up since the mdlc internal operating clocks are kept running. when mdlc wait mode is entered, the analog circuitry within the transmitter will be put into a power conserving ?leep?mode. in mdlc wait mode the mdlc can neither do wave shaping nor drive any data. therefore, it is important the programmer ensures that all transmissions are complete or aborted before putting the mdlc into mdlc stop or mdlc wait mode. 15.7.7 controlling external voltage regulators if the application node contains other, off-chip, supply voltage regulators that need to be controlled by j1850 network activity then an output port pin of the mcu must be reserved by the programmer for use as a power sense (psen) signal. this pin will provide a logical indication of when the mdlc is active through software. whenever the mcu is in the normal (run) mode of operation, the programmer should assert the psen output on the chosen port pin. the programmer should negate the psen output just prior to placing the microcontroller in the stop or wait mode.
section 15: message data link controller motorola page 131 mc68hc05v7 specification rev. 1.0 when the mdlc is in the mdlc stop or mdlc wait mode of operation, and network activity is sensed, a cpu interrupt request will be generated. as part of the service routine for this interrupt, the programmer should once again assert the psen output. note that both v cca and v dd for the mdlc must be maintained in the mdlc stop and mdlc wait modes of operation in order for this to work properly.
motorola section 15: message data link controller page 132 mc68hc05v7 specification rev. 1.0
section 16: instruction set motorola page 133 mc68hc05v7 specification rev. 1.0 section 16 instruction set the mcu has a set of 62 basic instructions. they can be divided into five different types: register/memory, read-modify-write, branch, bit manipulation, and control. the following paragraphs briefly explain each type. for more information on the instruction set, refer to the m6805 family user? manual (m6805um/ad3) or the associated mc68hc05 data sheet. 16.1 register/memory instructions most of these instructions use two operands. one operand is either the accumulator or the index register. the other operand is obtained from memory using one of the addressing modes. the jump unconditional (jmp) and jump to subroutine (jsr) instructions have no register operand. refer to the following instruction list. 16.2 read-modify-write instructions these instructions read a memory location or a register, modify or test its contents, and write the modified value back to memory or to the register. the test for negative or zero (tst) instruction is an exception to the read-modify-write sequence since it does not modify the value. do not use these read-modify-write instructions on write-only locations. refer to the following list of instructions. function load a from memory load x from memory store a in memory store x in memory add memory to a add memory and carry to a subtract memory subtract memory from a with borrow and memory to a or memory with a exclusive or memory with a arithmetic compare a with memory arithmetic compare x with memory bit test memory with a (logical compare) jump unconditional jump to subroutine mnemonic lda ldx sta stx add adc sub sbc and ora eor cmp cpx bit jmp jsr multiply mul
motorola section 16: instruction set page 134 mc68hc05v7 specification rev. 1.0 16.3 branch instructions this set of instructions branches if a particular condition is met; otherwise, no operation is performed. branch instructions are 2-byte instructions. refer to the following list for branch instructions. 16.4 bit manipulation instructions the mcu is capable of setting or clearing any read/write bit that resides in the first 256 bytes of the memory space where all port registers, port ddrs, timer, timer control, and on- chip ram reside. an additional feature allows the software to test and branch on the state of any bit within these 256 locations. the bit set, bit clear, and bit test and branch functions are each implemented with a single instruction. for test and branch instructions, the value function mnemonic increment inc decrement dec clear clr complement com negate (two? complement) neg rotate left thru carry rol rotate right thru carry ror logical shift left lsl logical shift right lsr arithmetic shift right asr test for negative or zero tst function mnemonic branch always bra branch never brn branch if higher bhi branch if lower or same bls branch if carry clear bcc branch if higher or same bhs branch if carry set bcs branch if lower blo branch if not equal bne branch if equal beq branch if half carry clear bhcc branch if half carry set bhcs branch if plus bpl branch if minus bmi branch if interrupt mask bit is clear bmc branch if interrupt mask bit is set bms branch if interrupt line is low bil branch if interrupt line is high bih branch to subroutine bsr
section 16: instruction set motorola page 135 mc68hc05v7 specification rev. 1.0 of the bit tested is also placed in the carry bit of the condition code register. the bit set and bit clear instructions are also read-modify-write instructions and should not be used to manipulate write-only locations. refer to the following list for bit manipulation instructions. 16.5 control instructions these instructions are register reference instructions and are used to control processor operation during program execution. refer to the following list for control instructions. 16.6 addressing modes the mcu uses ten different addressing modes to provide the programmer with an opportunity to optimize the code for all situations. the various indexed addressing modes make it possible to locate data tables, code conversion tables, and scaling tables anywhere in the memory space. short indexed accesses are single byte instructions; the longest instructions (3 bytes) permit accessing tables throughout memory. short and long absolute addressing is also included. one- or 2-byte direct addressing instructions access all data bytes in most applications. extended addressing permits jump instructions to reach all memory. the term ?ffective address?(ea) is used in describing the various addressing modes. effective address is defined as the address from which the argument for an instruction is fetched or stored. function set bit n clear bit n mnemonic bset n (n = 0. . .7) bclr n (n = 0. . .7) branch if bit n is set branch if bit n is clear brset n (n = 0. . .7) brclr n (n = 0. . .7) function transfer a to x transfer x to a set carry bit clear carry bit mnemonic tax txa sec clc set interrupt mask bit sei clear interrupt mask bit cli software interrupt swi return from subroutine rts return from interrupt rti reset stack pointer rsp no-operation nop wait wait stop stop
motorola section 16: instruction set page 136 mc68hc05v7 specification rev. 1.0 16.6.1 immediate in the immediate addressing mode, the operand is contained in the byte immediately following the opcode. the immediate addressing mode is used to access constants that do not change during program execution (for example, a constant used to initialize a loop counter). 16.6.2 direct in the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. direct addressing allows the user to directly address the lowest 256 bytes in memory with single 2-byte instructions. 16.6.3 extended in the extended addressing mode, the effective address of the argument is contained in the 2 bytes following the opcode byte. instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single 3-byte instruction. when using the motorola assembler, the user need not specify whether an instruction uses direct or extended addressing. the assembler automatically selects the shortest form of the instruction. 16.6.4 relative the relative addressing mode is only used in branch instructions. in relative addressing, the contents of the 8-bit signed offset byte (which is the last byte of the instruction) is added to the pc if, and only if, the branch conditions are true. otherwise, control proceeds to the next instruction. the span of relative addressing is from -128 to +127 from the address of the next opcode. the programmer need not calculate the offset when using the motorola assembler, since it calculates the proper offset and checks to see that it is within the span of the branch. 16.6.5 indexed, no offset in the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index register. this addressing mode can access the first 256 memory locations. these instructions are only 1 byte long. this mode is often used to move a pointer through a table or to hold the address of a frequently referenced ram or i/o location. 16.6.6 indexed, 8-bit offset in the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the unsigned byte following the opcode. the addressing mode is useful for selecting the kth element in an element table. with this 2-byte instruction, k would typically be in x with the address of the beginning of the table in the instruction. as such, tables may begin anywhere within the first 256 addressable locations and could extend as far as location 510. $1fe is the highest location that can be accessed in this way.
section 16: instruction set motorola page 137 mc68hc05v7 specification rev. 1.0 16.6.7 indexed, 16-bit offset in the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. this address mode can be used in a manner similar to indexed, 8-bit offset except that this 3-byte instruction allows tables to be anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. 16.6.8 bit set/clear in the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode, and the byte following the opcode specifies the direct address of the byte in which the specified bit is to be set or cleared. any read/write register bit in the first 256 locations of memory, including i/o, can be selectively set or cleared with a single 2-byte instruction. 16.6.9 bit test and branch the bit test and branch addressing mode is a combination of direct addressing and relative addressing. the bit that is to be tested and its condition (set or clear), is included in the opcode. the address of the byte to be tested is in the single byte immediately following the opcode byte. the signed relative 8-bit offset in the third byte is added to the pc if the specified bit is set or cleared in the specified memory location. this single 3-byte instruction allows the program to branch based on the condition of any readable bit in the first 256 locations of memory. the span of branching is from -128 to +127 from the address of the next opcode. the state of the tested bit is also transferred to the carry bit of the condition code register. 16.6.10 inherent in the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. operations specifying only the index register and/or accumulator as well as the control instructions with no other arguments are included in this mode. these instructions are 1 byte long.
motorola section 16: instruction set page 138 mc68hc05v7 specification rev. 1.0
section 17: electrical specifications motorola page 139 mc68hc05v7 specification rev. 1.0 section 17 electrical specifications 17.1 maximum ratings (voltages referenced to v ss ) this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd ). 17.2 thermal characteristics storage temperature range t stg -65 to +150 o c xx=b for sdip, xx=fn for plcc, xx=fu for qfp supply voltage unit value symbol rating v -0.5 to +42.0 v batt input voltage v in v current drain per pin excluding v dd and v ss 25 ma i operating temperature range t l to t h o c t a 0 to +70 mc68hc05v7xx (standard) mc68hc05v7cxx (extended) -40 to +85 v ss -0.3 to v dd +0.3 write/erase cycles (@ 10 ms write time & -40 c, +25 c, +85 c) 10,000 cycles data retention eeprom 10 years 60 thermal resistance sdip (56 pin) o c/w unit value symbol characteristic q ja 50 plcc (68 pin) o c/w q ja 85 qfp (64 pin) o c/w q ja
motorola section 17: electrical specifications page 140 mc68hc05v7 specification rev. 1.0 17.3 dc electrical characteristics (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = -40 c to +85 c, unless otherwise noted) (i load = -0.8 ma) pa0-7, pb0-7, pc0-7, pf0-3, pwm output voltage i load = 10.0 m a unit max typ min symbol characteristic v 0.1 v ol v dd -0.1 v oh output high voltage v dd -0.8 v oh v output low voltage (i load = 1.6 ma) pa0-7, pb0-7, pc0-7, pf0-3,pwm input high voltage v dd v batt v ih ports a, b, c v ign v input low voltage v il ports a, b, c v ign v v ss v ss 0.4 --- v ol v --- --- --- --- i dd i dd v dd supply current (see notes) ma run ma wait spi, timer, a/d, pwm, cop, and lvr enabled stop (regulator disabled, lvr enabled) 25 c 0 c to +70 c (standard) -40 c to +85 c (extended) i dd i dd i dd --- tbd tbd 200 3 5 --- --- --- tbd tbd m a m a m a i/o ports hi-z leakage current 1 i il pa0-7, pb0-7, pc0-7, pf0-3 m a input current 1 i in reset , ir q , osc1, tcap, pd0-7,pe0-7, ss m a capacitance * 12 c out ports (as input or output) pf rese t , ir q , osc1, osc2, tcap, pd0-7,pe0-7, ss c in ? ?f low voltage reset inhibit 4.2 v lvri v 3.5 low voltage reset recover 4.5 v lvrr v 3.6 low voltage reset inhibit/recover hysteresis 0.3 0.2 h lvr v 0.1 --- i batt v batt supply current at 12v 25 tbd m a --- i batt 800 tbd m a --- i batt 250 tbd m a stop regulator disabled stop regulator enabled (includes stop i dd , lvr disabled) run regulator disabled (transceiver current) --- ma wait above modules off i dd 1.2 --- 25 c (lvr disabled) i dd --- 100 --- m a input high voltage v dd v ih ports d, e, f, irq , reset , osc1 v 0. 7 v dd input low voltage 0. 3 v dd 0. 3 v batt v il ports d, e, f, ir q , reset , osc1 v v ss v ss 0. 8 v dd 0. 8 v batt 0. 4 v dd 0. 4 v batt
section 17: electrical specifications motorola page 141 mc68hc05v7 specification rev. 1.0 17.4 regulator electrical characteristics (v batt = 12 vdc 10%, v ss = 0 vdc, t a = -40 c to +85 c, unless otherwise noted) notes: (all values shown reflect average measurements.) 1. maximum voltage of 26.5v for 5 minutes only. if v batt exceeds v battmax , v dd may deviate from min/max limits. 2. guaranteed by design. not tested in productions tests. 3. this is the available current out of the v dd pin for off chip usage. 4. this transient may be disruptive but will not be destructive. 5. total regulator load of 20ma. lighter load currents result in lower v diff . * max i dd of 20ma at v dd =3.5v. symbol characteristic min max units v 16 v batt input voltage 1 8 v 40 v battmax maximum input voltage transient amplitude 2,4 26.5 ms 200 v battdur maximum input voltage transient duration 2,4 -- ua tbd i bias input bias current tbd uvrms tbd v n output noise voltage 2 - db 65 rr ripple rejection ratio 2 - v 2.5 v diff input - output differential voltage 5 v batt to v dd with v batt < min. 1.5* ma 95 i short short circuit current limit 75 mv/ c tbd t c temperature coefficient 2 - ma 20 i o output current 3 - v 5.25 v dd output voltage 4.75 mv 50 v linereg line regulation - mv 50 v loadreg load regulation at 20ma - notes: 1. all values shown reflect average measurements. 2. typical values at midpoint of voltage range, 25 c only. 3. run (operating) i dd , wait i dd : measured using external square wave clock source to osc1 (f osc = 4.2 mhz), all inputs 0.2 vdc from rail; no dc loads, less than 50 pf on all outputs, c l = 20 pf on osc2. 4. wait, stop i dd : all ports configured as inputs, v il = 0.2 vdc, v ih = v dd -0.2 vdc. 5. stop i dd measured with osc1 = v ss . 6. wait i dd is affected linearly by the osc2 capacitance. 7. total * not tested. v dd slew rate rising * 0.1 s vddr v/ m s v dd slew rate falling* 0.05 s vddf v/ m s por reset voltage * 100 v por mv
motorola section 17: electrical specifications page 142 mc68hc05v7 specification rev. 1.0 17.5 control timing (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = -40 c to +85 c, unless otherwise noted) notes: 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h 2. the 2-bit timer prescaler is the limiting factor in determining timer resolution. 3. the minimum period t ilil or t ihih should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc . 4. the minimum period t tltl should not be less than the number of cycles it takes to execute the capture interrupt service routine plus 24 t cyc . symbol characteristic min max ns --- t osc1 osc1 pulse width 90 t cyc --- t ihih pa0-7, pc0-7 interrupt pulse period note 3 ns --- t ihil pa0-7, pc0-7 interrupt pulse width high (edge-triggered) 120 t cyc --- t ilil irq interrupt pulse period (see figure 8-1) note 3 ns --- t rl reset pulse width low (see figure 8-1) 120 t cyc tbd t ilch stop recovery startup time (crystal oscillator option) --- t cyc tbd t oxon crystal oscillator startup time (crystal oscillator option) --- ns --- t cyc cycle time (1 ? f op ) 476 mhz mhz f op f op internal operating frequency crystal oscillator (f osc ? 2) external clock (f osc ? 2) --- dc 2.1 2.1 units mhz mhz 4.2 4.2 f osc f osc frequency of operation crystal oscillator option external clock source 0.1 dc ns --- t ilhi irq interrupt pulse width low (edge-triggered) 120 ms --- t eepgm eeprom programming time per byte 10 ms --- t ebyt eeprom erase time per byte 10 ms --- t eblock eeprom erase time per block 10 m s 10 t fpv eeprom programming voltage discharge period m s 5.0 t rcon rc oscillator stabilization time -- ms --- t ebulk eeprom bulk erase time 10 16-bit timer resolution (note 2) input capture pulse width (see figure 11-4) input capture period t cyc ns t cyc t resl t th, t tl t tltl 4.0 125 note 4 -- -- --
section 17: electrical specifications motorola page 143 mc68hc05v7 specification rev. 1.0 17.6 a/d converter characteristics (v cca = 5.0 vdc 10%, v ssa1 = 0 vdc, t a = -40 c to +85 c, unless otherwise noted) *t ad = t cyc if clock source equals mcu. comments unit max min characteristic bits 8 8 resolution absolute accuracy lsb 1 1 /2 (v refl = 0 v, v refh = v dd ) conversion range v v refl v refh a/d accuracy may decrease proportionately as v refh is reduced below 4.0 v dd v refl -0.1 v refh v v v refl v refh m s 100 power-up time input leakage m a pd0-pd7, pe0-pe7 1 v refl ,v refh 1 m a conversion time t ad * 32 32 (includes sampling time) inherent (within total error) monotonicity hex 01 00 zero input reading v in = 0v hex ff fe full-scale reading v in = v refh t ad * 12 12 sample time pf 8 input capacitance v v refh v refl analog input voltage including quantization m s 100 a/d on current stabilization time (t adon ) m s 5 rc oscillator stabilization time (t rcon ) not tested
motorola section 17: electrical specifications page 144 mc68hc05v7 specification rev. 1.0 17.7 dc electrical characteristics (v dd =3.5-4.5 vdc 10% 9 , v ss =0 vdc, t a =-40 c to +85 c, unless otherwise noted) notes: 1. all values shown reflect average measurements. 2. typical values at midpoint of voltage range, 25 c only. 3. wait i dd : only timer system active. 4. run (operating) i dd , wait i dd : measured using external square wave clock source (f osc =4.2 mhz), all inputs 0.2 v from rail; no dc loads, less than 50 pf on all outputs, c l =20 pf on osc2. 5. wait, stop i dd : all ports configured as inputs, v il =0.2 v, v ih =v dd -0.2 v. 6. stop i dd measured with osc1=v ss . 7. wait i dd is affected linearly by the osc2 capacitance. 8. the mdlc will not operate below 4.65 volts. * not tested. unit max typ min symbol characteristic v 0.1 v ol output voltage v dd -0.1 v oh output high voltage v dd -0.3 v oh (i load = -0.2 ma) pa0-7, pb0-7,pc0-7,pf0-3,pwm v output low voltage 0.3 v ol (i load = 0.4 ma) pa0-7, pb0-7,pc0-7,pf0-3,pwm v input high voltage v dd v ih ports a, b, c v 0.8 v dd input high voltage v dd v ih ports d, e,f, ir q, r eset , osc1 v 0.7xv dd i/o ports hi-z leakage current 1 i oz pa0-7, pb0-7, pc0-7, pf0-3 m a input current 1 i in rese t , ir q , osc1, tcap,ss m a pd0-pd7,pe0-7 i in 1 m a capacitance * 12 c out ports (as input or output) pf rese t , irq , osc1,osc2,tcap,ss c in ? ?f v i load = 10.0 m a tbd tbd tbd tbd i dd i dd v dd supply current (see notes) ma run ma wait spi, timer, a/d, pwm, cop and lvr enabled stop (regulator disabled, lvr enabled) 25 c 0 c to +70 c (standard) -40 c to +85 c (extended) i dd i dd i dd tbd tbd tbd tbd tbd tbd --- --- --- tbd tbd m a m a m a tbd ma wait above modules off i dd tbd --- 25 c (lvr disabled) i dd tbd tbd --- m a input low voltage 0.4xv dd v il ports a, b, c v v ss input low voltage 0.3 v dd v il ports d, e,f, irq , reset , osc1 v v ss
section 17: electrical specifications motorola page 145 mc68hc05v7 specification rev. 1.0 17.8 control timing (v dd =3.5-4.5 vdc 10%, v ss = 0 vdc, t a = -40 c to +85 c, unless otherwise noted) notes: 1. the 2-bit timer prescaler is the limiting factor in determining timer resolution. 2. the minimum period t ilil or t ihih should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc . 3. the minimum period t tltl should not be less than the number of cycles it takes to execute the capture interrupt service routine plus 24 t cyc . symbol characteristic min max ns --- t osc1 osc1 pulse width 90 t cyc --- t ihih pa0-7, pc0-7 interrupt pulse period note 3 ns --- t ihil pa0-7, pc0-7 interrupt pulse width high (edge-triggered) 120 t cyc --- t ilil irq interrupt pulse period note 3 ns --- t ilih irq interrupt pulse width low (edge-triggered) 120 t cyc --- t rl reset pulse width low 1.5 t cyc tbd t ilch stop recovery startup time (crystal oscillator option) --- t cyc tbd t oxon crystal oscillator startup time (crystal oscillator option) --- ns --- t cyc cycle time (1 ? f op ) 476 mhz mhz f op f op internal operating frequency crystal oscillator (f osc ? 2) external clock (f osc ? 2) --- dc 2.1 2.1 units mhz mhz 4.2 4.2 f osc f osc frequency of operation crystal oscillator option external clock source 0.1 dc ms --- t eepgm eeprom programming time per byte 15 ms --- t ebyt eeprom erase time per byte 15 ms --- t eblock eeprom erase time per block 15 m s 10 t fpv eeprom programming voltage discharge period m s 5.0 t rcon rc oscillator stabilization time -- ms --- t ebulk eeprom bulk erase time 15 16-bit timer resolution (note 2) input capture pulse width (see figure 11-4) input capture period t cyc ns t cyc t resl t th, t tl t tltl 4.0 250 note 4 -- -- --
motorola section 17: electrical specifications page 146 mc68hc05v7 specification rev. 1.0 17.9 lvr timing diagram t vddf = v dd /s vddf t vddr= v dd /s vdd r v lvri v lvrr v dd internal lvr reset pin
section 17: electrical specifications motorola page 147 mc68hc05v7 specification rev. 1.0 17.10 spi timing
motorola section 17: electrical specifications page 148 mc68hc05v7 specification rev. 1.0 serial peripheral interface (spi) timing (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) * signal production depends on software. ** assumes 200 pf load on all spi pins. num characteristic symbol min max unit operating frequency master slave f op ( m ) f op ( s ) dc dc 0.5 4.2 f op mhz 1 cycle time master slave t cyc ( m ) t cyc ( s ) 2.0 240 t cyc ns 2 enable lead time master slave t lead ( m ) t lead(s) * 240 ns ns 3 enable lag time master slave t lag ( m ) t lag ( s ) * 240 ns ns 4 clock (sck) high time master slave t w (sckh) m t w (sckh) s 340 190 ns ns 5 clock (sck) low time master slave t w (sckl) m t w (sckl) s 340 190 ns ns 6 data setup time (inputs) master slave t su ( m ) t su ( s ) 100 100 ns ns 7 data hold time (inputs) master slave t h ( m ) t h ( s ) 100 100 ns ns 8 access time (time to data active from high- impedance state) slave t a 0 120 ns 9 disable time (hold time to high-impedance state) slave t dis 240 ns 10 data valid (after enable edge)** t v ( s ) 240 ns 11 data hold time (output) (after enable edge) t ho 0ns 12 rise time (20% v dd to 70% v dd , c l =200 pf) spi outputs (sck, mosi, and miso) spi inputs (sck, mosi, miso, and ss ) t rm t rs 100 2.0 ns us 13 fall time (70% v dd to 20% v dd , c l =200 pf) spi outputs (sck, mosi, and miso) spi inputs (sck, mosi, miso, and ss ) t fm t fs 100 2.0 ns us
section 17: electrical specifications motorola page 149 mc68hc05v7 specification rev. 1.0 figure 17-1: spi master timing (cpha = 0) figure 17-2: spi master timing (cpha = 1) 4 1 13 5 5 12 13 12 7 6 4 msb in lsb in bit 6 --- 1 bit 6 --- 1 master msb out master lsb out 10 (ref) 13 11 10 11 (ref) 12 see note see note note: this first clock edge is generated internally but is not seen at the sck pin. ss (input) sck (cpol=0) (output) sck (cpol=1) (output) miso (input) mosi (output) ss is held high on master 4 1 12 5 5 13 12 13 7 6 4 msb in lsb in bit 6 --- 1 bit 6 --- 1 master msb out master lsb out 10 (ref) 13 11 10 11 (ref) 12 see note see note note: this last clock edge is generated internally but is not seen at the sck pin. ss (input) sck (cpol=0) (output) sck (cpol=1) (output) miso (input) mosi (output) ss is held high on master
motorola section 17: electrical specifications page 150 mc68hc05v7 specification rev. 1.0 figure 17-3: spi slave timing (cpha = 0) figure 17-4: spi slave timing (cpha = 1) 4 1 12 5 5 13 13 4 bit 6 --- 1 slave lsb out slave msb out see note note: not defined but normally lsb of character previously transmitted. ss (input) sck (cpol=0) (input) sck (cpol=1) (input) miso (output) mosi (input) 7 6 8 9 2 2 11 10 lsb in msb in bit 6 --- 1 12 11 4 1 12 5 5 13 12 13 4 bit 6 --- 1 slave msb out slave lsb out see note note: not defined but normally lsb of character previously transmitted. ss (input) sck (cpol=0) (input) sck (cpol=1) (input) miso (output) mosi (input) 7 6 10 8 2 3 9 11 10 lsb in msb in bit 6 --- 1
section 17: electrical specifications motorola page 151 mc68hc05v7 specification rev. 1.0 17.11 mdlc electrical specifications 17.11.1 absolute maximum ratings (voltages referenced to v ssa2 unless otherwise indicated.) 17.11.2 operating conditions (voltages referenced to v ssa2 ) 17.11.3 transmitter d.c. electrical characteristics (total network bus to v ssa2 resistance = 245 w to 15k w , v batt = 9 to 16v, v cca = 5.0v 5%, v ssa2 = 0v, t a = -40 c to +8 c, unless otherwise noted) rating symbol min. typ. max. unit battery voltage (v batt ) v batt -0.3 12.0 16.0 v reference supply voltage (v cca ) v cca -0.3 5.0 7.0 v bus voltage (bus) v bus -2.0 0 to 7.0 18.0 v transient voltage (v batt , bus, tbd max. time) v tran -2.0 +24.0 v bus voltage with respect to v batt v bus -- -- 10.0 v rating symbol min. typ. max. unit battery voltage (v batt ) for proper mdlc operation v batt 9.0 12.0 16.0 v battery supply current (run) i batt 5 50 ma battery supply current (stop) i batt 5 50 m a reference supply voltage (v cca ) v cca 4.75 5.00 5.25 v reference supply current (run) i cca 0.5 2 ma reference supply current (stop) i cca 40 50 m a characteristic symbol min. max. unit output high voltage (bus) v oh 6.25 8.0 v output low voltage (bus) v ol 0 1.5 v output current (bus, loss of v batt or v ssa2 , v out = 0v, v in = 0 to 8v) i out 1 ma output current (bus, tx = passive, v in = 12v) i out -200 ma output current (bus, tx = active, v in = 0v) i out 200 ma low voltage inhibit of transmitter for v batt v tivb 6.0 7.5 v low voltage inhibit of transmitter for v dd v rivd 4.5 4.75 v
motorola section 17: electrical specifications page 152 mc68hc05v7 specification rev. 1.0 17.11.4 transmitter a.c. electrical characteristics (v batt = 9 to 16v, v cca = 5.0v 5%, v ssa = 0v, t a = -40 c to +85 c, unless otherwise noted) 17.11.5 receiver d.c. electrical characteristics (v batt = 9 to 16v, v cca = 5.0v 5%, v ssa2 = 0 v, t a = -40 c to +85 c, unless otherwise noted) 17.11.6 transmitter vpw symbol timings (f mdlc = 1.048576 mhz, v batt = 12v, v cca = 5.0v, v ssa2 = 0v, t a = 25 c, unless otherwise noted) characteristic number symbol min. typ. max. unit transmitter rise time (rext1 = 31.6k w, rext2 = 24.9k w) 1 t r 13.0 14.5 16.0 m s transmitter fall time (rext1 = 31.6k w, rext2 = 24.9k w) 2 t f 13.0 14.5 16.0 m s characteristic symbol min. max. unit input high voltage (bus) v ih 4.25 v input low voltage (bus) v il 3.5 v input current (bus, normal operation, tx = passive, v in = 0 to 8v) i in 10 m a characteristic number symbol min. typ. max. unit passive logic 0 10 t tvp1 62.0 64.0 66.0 m s passive logic 1 11 t tvp2 126.0 128.0 130.0 m s active logic 0 12 t tva1 126.0 128.0 130.0 m s active logic 1 13 t tva2 62.0 64.0 66.0 m s start of frame (sof) 14 t tva3 198.0 200.0 202.0 m s figure 17-5: transmitter a.c. electrical characteristics bus 1 2 v oh 6.25 v 2 v v ol 0 v
section 17: electrical specifications motorola page 153 mc68hc05v7 specification rev. 1.0 17.11.7 receiver vpw symbol timings (f mdlc = 1.048576 mhz, v batt =12v, v cca = 5.0v, v ssa2 = 0 v, t a = 25 c, unless otherwise noted) note: the receiver symbol timing boundaries are subject to an uncertainty of 1 t mdlc m s due to sampling considerations. end of data (eod) 15 t tvp3 198.0 200.0 202.0 m s end of frame 16 t tv4 278.0 280.0 282.0 m s inter-frame separator (ifs) 17 t tv6 298.0 300.0 302.0 m s characteristic number symbol min. typ. max. unit passive logic 0 10 t rvp1 34.0 64.0 96.0 m s passive logic 1 11 t rvp2 96.0 128.0 163.0 m s active logic 0 12 t rva1 96.0 128.0 163.0 m s active logic 1 13 t rva2 34.0 64.0 96.0 m s start of frame (sof) 14 t rva3 163.0 200.0 239.0 m s end of data (eod) 15 t rvp3 163.0 200.0 239.0 m s end of frame 16 t rv4 239.0 280.0 320.0 m s break 18 t rv7 239.0 800.0 m s characteristic number symbol min. typ. max. unit
motorola section 17: electrical specifications page 154 mc68hc05v7 specification rev. 1.0 13 11 10 12 14 sof 15 18 "0" "0" "1" "1" eod brk "0" eof figure 17-6: variable pulse width modulation (vpw) symbol timings 16 17 ifs
section 18: 05v7 behavior during emulation motorola page 155 mc68hc05v7 specification rev. 1.0 section 18 05v7 behavior during emulation this section covers the functions of the mcu that behave differently during emulation using either the 705v8/05v7 evs or mmds emulation systems. since the 705v8/05v7 device itself is used in the emulator system and operates in test mode, some extra software operations must be performed to make the device behave as it will in the users application (user mode). the circuits which require special treatment are described in the sections that follow. 18.1 cop a value of $04 should be written to location $003f to enable the cop circuitry. the cop circuit is defaulted off to allow ease of factory testing. it should be noted that enabling the cop with this bit will enable the cop regardless of the state of the copen mask option. 18.2 mdlc the mdlc requires bit 2 and 3 to be set in the mdlc control register ($0e) to allow normal operation of the mdlc. if these two bits are not set during emulation the mdlc will not transmit or receive. 18.3 regulator the voltage regulator should not be enabled in the device used in the top board of the emulator system. this may result in a supply voltage contention and may overheat and damage the emulator system.
motorola section 18: 05v7 behavior during emulation page 156 mc68hc05v7 specification rev. 1.0

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